Re: [Freedreno] [PATCH 08/11] drm/msm/dpu: remove dpu_hw_pipe_cdp_cfg from dpu_plane

[abhinavk]

On 2021-09-30 06:59, Dmitry Baryshkov wrote:

Remove struct dpu_hw_pipe_cdp_cfg instance from dpu_plane, it is an
interim configuration structure. Allocate it on stack instead.

Signed-off-by: Dmitry Baryshkov <dmitry.barysh...@linaro.org>

Reviewed-by: Abhinav Kumar <abhin...@codeaurora.org>

---
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 14 +++++++-------
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h |  2 --
 2 files changed, 7 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index b8836c089863..d3ae0cb2047c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -1182,20 +1182,20 @@ static void
dpu_plane_sspp_atomic_update(struct drm_plane *plane)
                                pstate->multirect_index);

                if (pdpu->pipe_hw->ops.setup_cdp) {
-                       struct dpu_hw_pipe_cdp_cfg *cdp_cfg = &pstate->cdp_cfg;
+                       struct dpu_hw_pipe_cdp_cfg cdp_cfg;

-                       memset(cdp_cfg, 0, sizeof(struct dpu_hw_pipe_cdp_cfg));
+                       memset(&cdp_cfg, 0, sizeof(struct dpu_hw_pipe_cdp_cfg));

-                       cdp_cfg->enable = pdpu->catalog->perf.cdp_cfg
+                       cdp_cfg.enable = pdpu->catalog->perf.cdp_cfg
                                        [DPU_PERF_CDP_USAGE_RT].rd_enable;
-                       cdp_cfg->ubwc_meta_enable =
+                       cdp_cfg.ubwc_meta_enable =
                                        DPU_FORMAT_IS_UBWC(fmt);
-                       cdp_cfg->tile_amortize_enable =
+                       cdp_cfg.tile_amortize_enable =
                                        DPU_FORMAT_IS_UBWC(fmt) ||
                                        DPU_FORMAT_IS_TILE(fmt);
-                       cdp_cfg->preload_ahead = DPU_SSPP_CDP_PRELOAD_AHEAD_64;
+                       cdp_cfg.preload_ahead = DPU_SSPP_CDP_PRELOAD_AHEAD_64;

-                       pdpu->pipe_hw->ops.setup_cdp(pdpu->pipe_hw, cdp_cfg);
+                       pdpu->pipe_hw->ops.setup_cdp(pdpu->pipe_hw, &cdp_cfg);
                }
        }

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
index 087194be3c22..1ee5ca5fcdf7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
@@ -23,7 +23,6 @@
  * @multirect_index: index of the rectangle of SSPP
  * @multirect_mode: parallel or time multiplex multirect mode
  * @pending:   whether the current update is still pending
- * @cdp_cfg:   CDP configuration
  * @plane_fetch_bw: calculated BW per plane
  * @plane_clk: calculated clk per plane
  */
@@ -36,7 +35,6 @@ struct dpu_plane_state {
        uint32_t multirect_mode;
        bool pending;

-       struct dpu_hw_pipe_cdp_cfg cdp_cfg;
        u64 plane_fetch_bw;
        u64 plane_clk;
 };