Hi Vinod, I love your patch! Perhaps something to improve:
[auto build test WARNING on drm/drm-next] [also build test WARNING on v5.16-rc1 next-20211118] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Vinod-Koul/drm-msm-Add-Display-Stream-Compression-Support/20211116-142602 base: git://anongit.freedesktop.org/drm/drm drm-next config: arm64-randconfig-r036-20211118 (attached as .config) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # install arm64 cross compiling tool for clang build # apt-get install binutils-aarch64-linux-gnu # https://github.com/0day-ci/linux/commit/0d90631d88b4295b0612892e62110dd3b11c9d78 git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Vinod-Koul/drm-msm-Add-Display-Stream-Compression-Support/20211116-142602 git checkout 0d90631d88b4295b0612892e62110dd3b11c9d78 # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 ARCH=arm64 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <[email protected]> All warnings (new ones prefixed by >>): >> drivers/gpu/drm/msm/dsi/dsi_host.c:1039:13: warning: variable 'reg_ctrl' set >> but not used [-Wunused-but-set-variable] u32 reg, reg_ctrl, reg_ctrl2; ^ 1 warning generated. vim +/reg_ctrl +1039 drivers/gpu/drm/msm/dsi/dsi_host.c 924 925 static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 926 { 927 struct drm_display_mode *mode = msm_host->mode; 928 u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */ 929 u32 h_total = mode->htotal; 930 u32 v_total = mode->vtotal; 931 u32 hs_end = mode->hsync_end - mode->hsync_start; 932 u32 vs_end = mode->vsync_end - mode->vsync_start; 933 u32 ha_start = h_total - mode->hsync_start; 934 u32 ha_end = ha_start + mode->hdisplay; 935 u32 va_start = v_total - mode->vsync_start; 936 u32 va_end = va_start + mode->vdisplay; 937 u32 hdisplay = mode->hdisplay; 938 u32 wc; 939 940 DBG(""); 941 942 /* 943 * For bonded DSI mode, the current DRM mode has 944 * the complete width of the panel. Since, the complete 945 * panel is driven by two DSI controllers, the horizontal 946 * timings have to be split between the two dsi controllers. 947 * Adjust the DSI host timing values accordingly. 948 */ 949 if (is_bonded_dsi) { 950 h_total /= 2; 951 hs_end /= 2; 952 ha_start /= 2; 953 ha_end /= 2; 954 hdisplay /= 2; 955 } 956 957 if (msm_host->dsc) { 958 struct msm_display_dsc_config *dsc = msm_host->dsc; 959 960 /* update dsc params with timing params */ 961 dsi_dsc_update_pic_dim(dsc, mode->hdisplay, mode->vdisplay); 962 DBG("Mode Width- %d x Height %d\n", dsc->drm->pic_width, dsc->drm->pic_height); 963 964 /* we do the calculations for dsc parameters here so that 965 * panel can use these parameters 966 */ 967 dsi_populate_dsc_params(dsc); 968 969 /* Divide the display by 3 but keep back/font porch and 970 * pulse width same 971 */ 972 h_total -= hdisplay; 973 hdisplay /= 3; 974 h_total += hdisplay; 975 ha_end = ha_start + hdisplay; 976 } 977 978 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) { 979 if (msm_host->dsc) { 980 struct msm_display_dsc_config *dsc = msm_host->dsc; 981 u32 reg, intf_width, slice_per_intf; 982 u32 total_bytes_per_intf; 983 984 /* first calculate dsc parameters and then program 985 * compress mode registers 986 */ 987 intf_width = hdisplay; 988 slice_per_intf = DIV_ROUND_UP(intf_width, dsc->drm->slice_width); 989 990 dsc->drm->slice_count = 1; 991 dsc->bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width * 8, 8); 992 total_bytes_per_intf = dsc->bytes_in_slice * slice_per_intf; 993 994 dsc->eol_byte_num = total_bytes_per_intf % 3; 995 dsc->pclk_per_line = DIV_ROUND_UP(total_bytes_per_intf, 3); 996 dsc->bytes_per_pkt = dsc->bytes_in_slice * dsc->drm->slice_count; 997 dsc->pkt_per_line = slice_per_intf / dsc->drm->slice_count; 998 999 reg = dsc->bytes_per_pkt << 16; 1000 reg |= (0x0b << 8); /* dtype of compressed image */ 1001 1002 /* pkt_per_line: 1003 * 0 == 1 pkt 1004 * 1 == 2 pkt 1005 * 2 == 4 pkt 1006 * 3 pkt is not supported 1007 * above translates to ffs() - 1 1008 */ 1009 reg |= (ffs(dsc->pkt_per_line) - 1) << 6; 1010 1011 dsc->eol_byte_num = total_bytes_per_intf % 3; 1012 reg |= dsc->eol_byte_num << 4; 1013 reg |= 1; 1014 1015 dsi_write(msm_host, 1016 REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg); 1017 } 1018 1019 dsi_write(msm_host, REG_DSI_ACTIVE_H, 1020 DSI_ACTIVE_H_START(ha_start) | 1021 DSI_ACTIVE_H_END(ha_end)); 1022 dsi_write(msm_host, REG_DSI_ACTIVE_V, 1023 DSI_ACTIVE_V_START(va_start) | 1024 DSI_ACTIVE_V_END(va_end)); 1025 dsi_write(msm_host, REG_DSI_TOTAL, 1026 DSI_TOTAL_H_TOTAL(h_total - 1) | 1027 DSI_TOTAL_V_TOTAL(v_total - 1)); 1028 1029 dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC, 1030 DSI_ACTIVE_HSYNC_START(hs_start) | 1031 DSI_ACTIVE_HSYNC_END(hs_end)); 1032 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0); 1033 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS, 1034 DSI_ACTIVE_VSYNC_VPOS_START(vs_start) | 1035 DSI_ACTIVE_VSYNC_VPOS_END(vs_end)); 1036 } else { /* command mode */ 1037 if (msm_host->dsc) { 1038 struct msm_display_dsc_config *dsc = msm_host->dsc; > 1039 u32 reg, reg_ctrl, reg_ctrl2; 1040 u32 slice_per_intf, bytes_in_slice, total_bytes_per_intf; 1041 1042 reg_ctrl = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL); 1043 reg_ctrl2 = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2); 1044 1045 slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->drm->slice_width); 1046 bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width * 1047 dsc->drm->bits_per_pixel, 8); 1048 dsc->drm->slice_chunk_size = bytes_in_slice; 1049 total_bytes_per_intf = dsc->bytes_in_slice * slice_per_intf; 1050 dsc->pkt_per_line = slice_per_intf / dsc->drm->slice_count; 1051 1052 reg = 0x39 << 8; 1053 reg |= ffs(dsc->pkt_per_line) << 6; 1054 1055 dsc->eol_byte_num = total_bytes_per_intf % 3; 1056 reg |= dsc->eol_byte_num << 4; 1057 reg |= 1; 1058 1059 reg_ctrl |= reg; 1060 reg_ctrl2 |= bytes_in_slice; 1061 1062 dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg); 1063 dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2); 1064 } 1065 1066 /* image data and 1 byte write_memory_start cmd */ 1067 if (!msm_host->dsc) 1068 wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1; 1069 else 1070 wc = mode->hdisplay / 2 + 1; 1071 1072 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL, 1073 DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) | 1074 DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL( 1075 msm_host->channel) | 1076 DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE( 1077 MIPI_DSI_DCS_LONG_WRITE)); 1078 1079 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_TOTAL, 1080 DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(hdisplay) | 1081 DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(mode->vdisplay)); 1082 } 1083 } 1084 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/[email protected]
.config.gz
Description: application/gzip
