Hi Thomas,
Am 19.11.21 um 15:28 schrieb Thomas Hellström:
Hi, Christian,
We have an upcoming use-case in i915 where one solution would be
sparsely populated TTM bos.
We had that at one point where ttm_tt pages were allocated on demand,
but this time we'd rather be looking at multiple struct ttm_resources
per bo and those resources could be from different managers.
There might theoretically be other ways we can handle this use-case
but I wanted to check with you whether this is something AMD is
already looking into and if not, your general opinion.
oh, yes I've looked into this as well a very long time ago.
At that point the basic blocker was that we couldn't have different
cache setting for the same VMA, but I think that's fixed by now.
Another thing is that you essentially need to move the LRU handling into
the resource like I already planned to do anyway.
Regards,
Christian.
Thanks,
Thomas
