Re: [PATCH v3 06/13] drm/msm/disp/dpu1: Add DSC support in hw_ctl

[Dmitry Baryshkov]

On 16/11/2021 09:22, Vinod Koul wrote:

Later gens of hardware have DSC bits moved to hw_ctl, so configure these
bits so that DSC would work there as well

Signed-off-by: Vinod Koul <vk...@kernel.org>

Reviewed-by: Dmitry Baryshkov <dmitry.barysh...@linaro.org>

---
  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 11 ++++++++++-
  1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 36831457a91b..66b0c44118d8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -25,6 +25,8 @@
  #define   CTL_MERGE_3D_ACTIVE           0x0E4
  #define   CTL_INTF_ACTIVE               0x0F4
  #define   CTL_MERGE_3D_FLUSH            0x100
+#define   CTL_DSC_ACTIVE                0x0E8
+#define   CTL_DSC_FLUSH                0x104
  #define   CTL_INTF_FLUSH                0x110
  #define   CTL_INTF_MASTER               0x134
  #define   CTL_FETCH_PIPE_ACTIVE         0x0FC
@@ -34,6 +36,7 @@

#define DPU_REG_RESET_TIMEOUT_US 2000

  #define  MERGE_3D_IDX   23
+#define  DSC_IDX        22
  #define  INTF_IDX       31
  #define CTL_INVALID_BIT                 0xffff

@@ -120,7 +123,6 @@ static u32 dpu_hw_ctl_get_pending_flush(struct dpu_hw_ctl *ctx) static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx)

  {
-
        if (ctx->pending_flush_mask & BIT(MERGE_3D_IDX))
                DPU_REG_WRITE(&ctx->hw, CTL_MERGE_3D_FLUSH,
                                ctx->pending_merge_3d_flush_mask);
@@ -498,6 +500,9 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
        u32 intf_active = 0;
        u32 mode_sel = 0;

+ if (cfg->dsc)

+               DPU_REG_WRITE(&ctx->hw, CTL_DSC_FLUSH, cfg->dsc);
+
        if (cfg->intf_mode_sel == DPU_CTL_MODE_SEL_CMD)
                mode_sel |= BIT(17);

@@ -509,6 +514,10 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,

        if (cfg->merge_3d)
                DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE,
                              BIT(cfg->merge_3d - MERGE_3D_0));
+       if (cfg->dsc) {
+               DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, cfg->dsc);
+               DPU_REG_WRITE(c, CTL_DSC_ACTIVE, cfg->dsc);
+       }
  }

static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,

--
With best wishes
Dmitry