On Mon 22 Nov 05:26 CST 2021, Sankeerth Billakanti wrote:
> From: Krishna Manikandan <quic_mkri...@quicinc.com>
>
> Add DSI controller and PHY nodes for sc7280.
>
> Signed-off-by: Rajeev Nandan <quic_rajee...@quicinc.com>
> Signed-off-by: Krishna Manikandan <quic_mkri...@quicinc.com>
> Reviewed-by: Matthias Kaehlcke <m...@chromium.org>
> Reviewed-by: Stephen Boyd <swb...@chromium.org>
> Signed-off-by: Sankeerth Billakanti <quic_sbill...@quicinc.com>
> ---
>
> Changes in v4:
> None
>
> Changes in v3:
> - Add the dsi_phy clocks (Kuogee Hsieh)
> - One clock cell per line (Stephen Boyd)
>
> Changes in v2:
> - Drop flags from interrupts (Stephen Boyd)
> - Rename dsi-opp-table (Stephen Boyd)
> - Rename dsi phy node (Stephen Boyd)
>
>
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 111
> ++++++++++++++++++++++++++++++++++-
> 1 file changed, 109 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index a4536b6..12c4d32 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -2691,8 +2691,14 @@
> reg = <0 0xaf00000 0 0x20000>;
> clocks = <&rpmhcc RPMH_CXO_CLK>,
> <&gcc GCC_DISP_GPLL0_CLK_SRC>,
> - <0>, <0>, <0>, <0>, <0>, <0>;
> - clock-names = "bi_tcxo", "gcc_disp_gpll0_clk",
> + <&dsi_phy 0>,
> + <&dsi_phy 1>,
> + <0>,
> + <0>,
> + <0>,
> + <0>;
> + clock-names = "bi_tcxo",
> + "gcc_disp_gpll0_clk",
> "dsi0_phy_pll_out_byteclk",
> "dsi0_phy_pll_out_dsiclk",
> "dp_phy_pll_link_clk",
> @@ -2768,6 +2774,18 @@
>
> status = "disabled";
>
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dpu_intf1_out: endpoint {
> + remote-endpoint =
> <&dsi0_in>;
> + };
> + };
> + };
> +
> mdp_opp_table: opp-table {
> compatible = "operating-points-v2";
>
> @@ -2792,6 +2810,95 @@
> };
> };
> };
> +
> + dsi0: dsi@ae94000 {
Please label this mdss_dsi0, to make it group nicely when sorted in the
dts.
> + compatible = "qcom,mdss-dsi-ctrl";
> + reg = <0 0x0ae94000 0 0x400>;
> + reg-names = "dsi_ctrl";
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <4>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
> + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
> + <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
> + <&dispcc DISP_CC_MDSS_ESC0_CLK>,
> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&gcc GCC_DISP_HF_AXI_CLK>;
> + clock-names = "byte",
> + "byte_intf",
> + "pixel",
> + "core",
> + "iface",
> + "bus";
> +
> + operating-points-v2 = <&dsi_opp_table>;
> + power-domains = <&rpmhpd SC7280_CX>;
> +
> + phys = <&dsi_phy>;
> + phy-names = "dsi";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dsi0_in: endpoint {
> + remote-endpoint =
> <&dpu_intf1_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dsi0_out: endpoint {
> + };
> + };
> + };
> +
> + dsi_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-187500000 {
> + opp-hz = /bits/ 64 <187500000>;
> + required-opps =
> <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-300000000 {
> + opp-hz = /bits/ 64 <300000000>;
> + required-opps =
> <&rpmhpd_opp_svs>;
> + };
> +
> + opp-358000000 {
> + opp-hz = /bits/ 64 <358000000>;
> + required-opps =
> <&rpmhpd_opp_svs_l1>;
> + };
> + };
> + };
> +
> + dsi_phy: phy@ae94400 {
Why is above "dsi0" when this is "dsi_phy", drop the 0 on dsi0?
Also, please label this mdss_dsi_phy.
Thanks,
Bjorn
> + compatible = "qcom,sc7280-dsi-phy-7nm";
> + reg = <0 0x0ae94400 0 0x200>,
> + <0 0x0ae94600 0 0x280>,
> + <0 0x0ae94900 0 0x280>;
> + reg-names = "dsi_phy",
> + "dsi_phy_lane",
> + "dsi_pll";
> +
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "iface", "ref";
> +
> + status = "disabled";
> + };
> };
>
> pdc: interrupt-controller@b220000 {
> --
> 2.7.4
>
