Quoting Rajeev Nandan (2021-12-30 01:24:35)
> Add 10nm dsi phy tuning properties for phy drive strength and
> phy drive level adjustemnt.
s/adjustemnt/adjustment/
Please add the details about parasitics and eye shape tuning to this
commit text.
>
> Signed-off-by: Rajeev Nandan <quic_rajee...@quicinc.com>
> ---
> .../devicetree/bindings/display/msm/dsi-phy-10nm.yaml | 19
> +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml
> b/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml
> index 4399715..9406982 100644
> --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml
> +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml
> @@ -35,6 +35,18 @@ properties:
> Connected to DSI0_MIPI_DSI_PLL_VDDA0P9 pin for sc7180 target and
> connected to VDDA_MIPI_DSI_0_PLL_0P9 pin for sdm845 target
>
> + phy-drive-strength-cfg:
> + type: array
> + description:
> + Register values of DSIPHY_RESCODE_OFFSET_TOP and
> DSIPHY_RESCODE_OFFSET_BOT
> + for all five lanes to adjust the phy drive strength.
> +
> + phy-drive-level-cfg:
> + type: array
> + description:
> + Register values of DSIPHY_RESCODE_OFFSET_TOP for all five lanes to
> adjust
> + phy drive level/amplitude.
It would be better to put human understandable values into DT here. This
looks like a black box to anyone outside of qcom, so they won't know how
to tune or set these register values.
At least for phy-drive-level-cfg it sounds like it could be some sort of
property that is a u32 array of 5 elements for each lane indicating some
sort of amplitude, i.e.
phy-max-amplitudes = <0 1 2 3 4>;
phy-min-amplitudes = <0 1 2 3 4>;
where each index corresponds to a particular lane. Then the driver can
parse the amplitude and convert it into some sort of register value.
