+CC: dri-devel
On 10.01.2022 16:27, Jagan Teki wrote:
TM2 board DSI pipeline has input from MIC and output to
s6e3ha2 panel.
The existing pipeline has child nodes of ports, panel and
MIC is remote-endpoint reference of port@0 of ports.
Adding panel as another child node to DSI is unconventional
as pipeline has ports child. However it can be true if MIC
is added inside port node like this.
dsi {
compatible = "samsung,exynos5433-mipi-dsi";
#address-cells = <1>;
#size-cells = <0>;
port {
dsi_to_mic: endpoint {
remote-endpoint = <&mic_to_dsi>;
};
};
panel@0 {
compatible = "samsung,s6e3hf2";
reg = <0>;
vdd3-supply = <&ldo27_reg>;
vci-supply = <&ldo28_reg>;
reset-gpios = <&gpg0 0 GPIO_ACTIVE_LOW>;
enable-gpios = <&gpf1 5 GPIO_ACTIVE_HIGH>;
};
};
The above pipeline is proper but it requires the DSI input MIC
pipeline to update.
This patch is trying to add panel at port@1 so-that the entire
pipeline before to panel output is untouched.
Reported-by: Marek Szyprowski <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
---
arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
index aca01709fd29..e13210c8d7e0 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
@@ -53,6 +53,16 @@ &cmu_disp {
};
&dsi {
+ ports {
+ port@1 {
+ reg = <1>;
+
+ dsi_out_panel: endpoint {
+ remote-endpoint = <&dsi_in_panel>;
+ };
+ };
+ };
+
panel@0 {
compatible = "samsung,s6e3ha2";
reg = <0>;
@@ -60,6 +70,12 @@ panel@0 {
vci-supply = <&ldo28_reg>;
reset-gpios = <&gpg0 0 GPIO_ACTIVE_LOW>;
enable-gpios = <&gpf1 5 GPIO_ACTIVE_HIGH>;
+
+ port {
+ dsi_in_panel: endpoint {
+ remote-endpoint = <&dsi_out_panel>;
+ };
+ };
As I already wrote in Exynos thread, DSI host has already parent-child
relation with the panel - DSI host knows well who is connected to it.
Adding another links between them is redundant and has no value added.
I have already answered in Exynos thread[1] how could you deal with the
issue, you have.
[1]:
https://lore.kernel.org/dri-devel/[email protected]/
Regards
Andrzej
};
};
