On Fri, Feb 18, 2022 at 12:12:21AM +0530, Ramalingam C wrote:
From: Matt Roper <matthew.d.ro...@intel.com>
DG2 supports a 5th display output which the hardware refers to as "TC1,"
even though it isn't a Type-C output. This behaves similarly to the TC1
on past platforms with just a couple minor differences:
* DG2's TC1 bit in SDEISR is at bit 25 rather than 24 as it is on
ICP/TGP/ADP.
* DG2 doesn't need the hpd inversion setting that we had to use on DG1
v2:
intel_ddi_init(dev_priv, PORT_TC1); [Matt]
Cc: Swathi Dhanavanthri <swathi.dhanavant...@intel.com>
Cc: Lucas De Marchi <lucas.demar...@intel.com>
Cc: José Roberto de Souza <jose.so...@intel.com>
Signed-off-by: Matt Roper <matthew.d.ro...@intel.com>
Signed-off-by: Ramalingam C <ramalinga...@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demar...@intel.com>
Lucas De Marchi
