[PATCH v3 1/4] drm/i915/gt: Explicitly clear BB_OFFSET for new contexts

[Ramalingam C]

From: Chris Wilson <ch...@chris-wilson.co.uk>

Even though the initial protocontext we load onto HW has the register
cleared, by the time we save it into the default image, BB_OFFSET has
had the enable bit set. Reclear BB_OFFSET for each new context.

Testcase: igt/i915_selftests/gt_lrc

v2:
  Extend it for gen8.

Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com>
Signed-off-by: Ramalingam C <ramalinga...@intel.com>
Reviewed-by: Thomas Hellstrom <thomas.hellst...@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine_regs.h |  1 +
 drivers/gpu/drm/i915/gt/intel_lrc.c         | 19 +++++++++++++++++++
 drivers/gpu/drm/i915/gt/selftest_lrc.c      |  5 +++++
 3 files changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_regs.h 
b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
index 594a629cb28f..d4b02d36d2a6 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
@@ -109,6 +109,7 @@
 #define RING_SBBSTATE(base)                    _MMIO((base) + 0x118) /* hsw+ */
 #define RING_SBBADDR_UDW(base)                 _MMIO((base) + 0x11c) /* gen8+ 
*/
 #define RING_BBADDR(base)                      _MMIO((base) + 0x140)
+#define RING_BB_OFFSET(base)                   _MMIO((base) + 0x158)
 #define RING_BBADDR_UDW(base)                  _MMIO((base) + 0x168) /* gen8+ 
*/
 #define CCID(base)                             _MMIO((base) + 0x180)
 #define   CCID_EN                              BIT(0)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c 
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 3f83a9038e13..5f6479dadea7 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -662,6 +662,20 @@ static int lrc_ring_mi_mode(const struct intel_engine_cs 
*engine)
                return -1;
 }
 
+static int lrc_ring_bb_offset(const struct intel_engine_cs *engine)
+{
+       if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
+               return 0x80;
+       else if (GRAPHICS_VER(engine->i915) >= 12)
+               return 0x70;
+       else if (GRAPHICS_VER(engine->i915) >= 9)
+               return 0x64;
+       else if (GRAPHICS_VER(engine->i915) >= 8)
+               return 0xc4;
+       else
+               return -1;
+}
+
 static int lrc_ring_gpr0(const struct intel_engine_cs *engine)
 {
        if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
@@ -768,6 +782,7 @@ static void init_common_regs(u32 * const regs,
                             bool inhibit)
 {
        u32 ctl;
+       int loc;
 
        ctl = _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH);
        ctl |= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
@@ -779,6 +794,10 @@ static void init_common_regs(u32 * const regs,
        regs[CTX_CONTEXT_CONTROL] = ctl;
 
        regs[CTX_TIMESTAMP] = ce->stats.runtime.last;
+
+       loc = lrc_ring_bb_offset(engine);
+       if (loc != -1)
+               regs[loc + 1] = 0;
 }
 
 static void init_wa_bb_regs(u32 * const regs,
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c 
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 6ba52ef1acb8..33f22f17e358 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -323,6 +323,11 @@ static int live_lrc_fixed(void *arg)
                                lrc_ring_cmd_buf_cctl(engine),
                                "RING_CMD_BUF_CCTL"
                        },
+                       {
+                               
i915_mmio_reg_offset(RING_BB_OFFSET(engine->mmio_base)),
+                               lrc_ring_bb_offset(engine),
+                               "RING_BB_OFFSET"
+                       },
                        { },
                }, *t;
                u32 *hw;
-- 
2.20.1