Il 11/05/22 04:36, xinlei....@mediatek.com ha scritto:
From: Jitao Shi <jitao....@mediatek.com>To comply with the panel sequence, hold the mipi signal to LP00 before the dcs cmds transmission, and pull the mipi signal high from LP00 to LP11 until the start of the dcs cmds transmission. The normal panel timing is : (1) pp1800 DC pull up (2) avdd & avee AC pull high (3) lcm_reset pull high -> pull low -> pull high (4) Pull MIPI signal high (LP11) -> initial code -> send video data(HS mode) The power-off sequence is reversed. If dsi is not in cmd mode, then dsi will pull the mipi signal high in the mtk_output_dsi_enable function. The delay in lane_ready func is the reaction time of dsi_rx after pulling up the mipi signal. Fixes: 2dd8075d2185 ("drm/mediatek: mtk_dsi: Use the drm_panel_bridge API") Signed-off-by: Jitao Shi <jitao....@mediatek.com> Signed-off-by: Xinlei Lee <xinlei....@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delre...@collabora.com>
