Hi Marek,
thanks for the patch.
Reviewed-by: Yannick Fertre <[email protected]>
On 10/12/22 01:10, Marek Vasut wrote:
STM32MP15xx RM0436 Rev 6 "35.7.3 LTDC synchronization size configuration
register (LTDC_SSCR)" on page 1784 and onward indicates VSH and similar
bits are all [11:0] instead of [10:0] wide. Fix this.
[1] https://www.st.com/resource/en/reference_manual/DM00327659-.pdf
Fixes: b759012c5fa7 ("drm/stm: Add STM32 LTDC driver")
Signed-off-by: Marek Vasut <[email protected]>
---
Cc: Alexandre Torgue <[email protected]>
Cc: Antonio Borneo <[email protected]>
Cc: Benjamin Gaignard <[email protected]>
Cc: Maxime Coquelin <[email protected]>
Cc: Philippe Cornu <[email protected]>
Cc: Sam Ravnborg <[email protected]>
Cc: Vincent Abriou <[email protected]>
Cc: Yannick Fertre <[email protected]>
Cc: [email protected]
Cc: [email protected]
To: [email protected]
---
drivers/gpu/drm/stm/ltdc.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
index 03c6becda795c..639ed00b44a57 100644
--- a/drivers/gpu/drm/stm/ltdc.c
+++ b/drivers/gpu/drm/stm/ltdc.c
@@ -111,16 +111,16 @@
#define LTDC_L1FPF1R (ldev->caps.layer_regs[24]) /* L1 Flexible Pixel
Format 1 */
/* Bit definitions */
-#define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */
+#define SSCR_VSH GENMASK(11, 0) /* Vertical Synchronization Height */
#define SSCR_HSW GENMASK(27, 16) /* Horizontal Synchronization Width */
-#define BPCR_AVBP GENMASK(10, 0) /* Accumulated Vertical Back Porch */
+#define BPCR_AVBP GENMASK(11, 0) /* Accumulated Vertical Back Porch */
#define BPCR_AHBP GENMASK(27, 16) /* Accumulated Horizontal Back Porch */
-#define AWCR_AAH GENMASK(10, 0) /* Accumulated Active Height */
+#define AWCR_AAH GENMASK(11, 0) /* Accumulated Active Height */
#define AWCR_AAW GENMASK(27, 16) /* Accumulated Active Width */
-#define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */
+#define TWCR_TOTALH GENMASK(11, 0) /* TOTAL Height */
#define TWCR_TOTALW GENMASK(27, 16) /* TOTAL Width */
#define GCR_LTDCEN BIT(0) /* LTDC ENable */
