Currently, there are issues with enabling PSR-SU + DSC. This stems from
the fact that DSC imposes a slice height on transmitted video data and
we are not conforming to that slice height in PSR-SU regions. So, pass
slice_height into su_y_granularity to feed the DSC slice height into
PSR-SU code.

Signed-off-by: Hamza Mahfooz <hamza.mahf...@amd.com>
---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 38 +++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
index 26291db0a3cf..55acadf0b63f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
@@ -53,6 +53,41 @@ static bool link_supports_psrsu(struct dc_link *link)
        return true;
 }
 
+static bool psr_su_set_y_granularity(struct dc *dc, struct dc_link *link,
+                                    struct dc_stream_state *stream,
+                                    struct psr_config *config)
+{
+       u16 pic_height;
+       u8 slice_height;
+
+       if (!dc->caps.edp_dsc_support ||
+           link->panel_config.dsc.disable_dsc_edp ||
+           
!link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT ||
+           !stream->timing.dsc_cfg.num_slices_v)
+               return true;
+
+       pic_height = stream->timing.v_addressable +
+               stream->timing.v_border_top + stream->timing.v_border_bottom;
+       slice_height = pic_height / stream->timing.dsc_cfg.num_slices_v;
+
+       if (slice_height) {
+               if (config->su_y_granularity &&
+                   (slice_height % config->su_y_granularity)) {
+                       WARN(1,
+                            "%s: dsc: %d, slice_height: %d, num_slices_v: 
%d\n",
+                            __func__,
+                            
stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported,
+                            slice_height,
+                            stream->timing.dsc_cfg.num_slices_v);
+                       return false;
+               }
+
+               config->su_y_granularity = slice_height;
+       }
+
+       return true;
+}
+
 /*
  * amdgpu_dm_set_psr_caps() - set link psr capabilities
  * @link: link
@@ -122,6 +157,9 @@ bool amdgpu_dm_link_setup_psr(struct dc_stream_state 
*stream)
                psr_config.allow_multi_disp_optimizations =
                        (amdgpu_dc_feature_mask & DC_PSR_ALLOW_MULTI_DISP_OPT);
 
+               if (!psr_su_set_y_granularity(dc, link, stream, &psr_config))
+                       return false;
+
                ret = dc_link_setup_psr(link, stream, &psr_config, 
&psr_context);
 
        }
-- 
2.38.1

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