convert from number of lanes to register setting.
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/radeon/r600_dpm.c | 10 ++++++++++
drivers/gpu/drm/radeon/r600_dpm.h | 1 +
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/radeon/r600_dpm.c
b/drivers/gpu/drm/radeon/r600_dpm.c
index 34ea5d6..89c46c5 100644
--- a/drivers/gpu/drm/radeon/r600_dpm.c
+++ b/drivers/gpu/drm/radeon/r600_dpm.c
@@ -1246,3 +1246,13 @@ u16 r600_get_pcie_lane_support(struct radeon_device
*rdev,
return 16;
}
}
+
+u8 r600_encode_pci_lane_width(u32 lanes)
+{
+ u8 encoded_lanes[] = { 0, 1, 2, 0, 3, 0, 0, 0, 4, 0, 0, 0, 5, 0, 0, 0,
6 };
+
+ if (lanes > 16)
+ return 0;
+
+ return encoded_lanes[lanes];
+}
diff --git a/drivers/gpu/drm/radeon/r600_dpm.h
b/drivers/gpu/drm/radeon/r600_dpm.h
index 71d5d93..8dc1fbd 100644
--- a/drivers/gpu/drm/radeon/r600_dpm.h
+++ b/drivers/gpu/drm/radeon/r600_dpm.h
@@ -227,5 +227,6 @@ enum radeon_pcie_gen r600_get_pcie_gen_support(struct
radeon_device *rdev,
u16 r600_get_pcie_lane_support(struct radeon_device *rdev,
u16 asic_lanes,
u16 default_lanes);
+u8 r600_encode_pci_lane_width(u32 lanes);
#endif
--
1.8.3.1
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