On Tue, 07 Feb 2023, Arun R Murthy <arun.r.mur...@intel.com> wrote: > Enable SDP error detection configuration, this will set CRC16 in > 128b/132b link layer. > For Display version 13 a hardware bit31 in register VIDEO_DIP_CTL is > added to enable/disable SDP CRC applicable for DP2.0 only, but the > default value of this bit will enable CRC16 in 128b/132b hence > skipping this write. > Corrective actions on SDP corruption is yet to be defined. > > v2: Moved the CRC enable to link training init(Jani N) > v3: Moved crc enable to ddi pre enable <Jani N>
It's still in intel_dp_start_link_train()...? BR, Jani. > > Signed-off-by: Arun R Murthy <arun.r.mur...@intel.com> > --- > .../gpu/drm/i915/display/intel_dp_link_training.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c > b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > index 3d3efcf02011..7064e465423b 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > @@ -1453,4 +1453,16 @@ void intel_dp_start_link_train(struct intel_dp > *intel_dp, > > if (!passed) > intel_dp_schedule_fallback_link_training(intel_dp, crtc_state); > + > + /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */ > + if (intel_dp_is_uhbr(crtc_state) && passed) > + drm_dp_dpcd_writeb(&intel_dp->aux, > + DP_SDP_ERROR_DETECTION_CONFIGURATION, > + DP_SDP_CRC16_128B132B_EN); > + /* > + * VIDEO_DIP_CTL register bit 31 should be set to '0' to not > + * disable SDP CRC. This is applicable for Display version 13. > + * Default value of bit 31 is '0' hence discarding the write > + */ > + /* TODO: Corrective actions on SDP corruption yet to be defined > */ > } -- Jani Nikula, Intel Open Source Graphics Center
