According to the Allwinner A64's BSP code, the PLL rate needs to be set to the following frequency when using DSI: PLL rate = DCLK * bpp / lanes
Source: [1] The relevant lines for DSI (ommisions and comments mine): dclk_rate = lcdp->panel_info.lcd_dclk_freq * 1000000; lcd_rate = dclk_rate * clk_info.dsi_div; // dsi_div = bpp/lane pll_rate = lcd_rate * clk_info.lcd_div; // lcd_div = 1 --> pll_rate = lcd_rate dsi_rate = pll_rate / clk_info.dsi_div // --> dsi_rate = dclk_rate clk_set_rate(lcdp->clk_parent, pll_rate); This was already discussed by Maxime, Jagan and Michael in the past in the thread following this message: [2]. Unfortunately, there never was a conclusion in the form of code. The attached patch is a slight variation of a patch that is part of megi's kernel branch that many PinePhone distributions (e.g. postmarketOS) use [3]. It calculates the TCON clock rate by using the formula above and dividing it by SUN6I_DSI_TCON_DIV, in order to force the parent clock to be set to the correct rate. If I read the thread following this message [2] correctly, this was also what Maxime had in mind. Please also note that, unfortunately, I only have a single board and panel (namely the PinePhone) to test this on. Thanks, Frank [1] https://github.com/BPI-SINOVOIP/BPI-M64-bsp/blob/master/linux-sunxi/drivers/video/sunxi/disp2/disp/de/disp_lcd.c#L781 [2] https://lore.kernel.org/lkml/camty3zash2iz+jeqte3d58axfguhmsg9yoo56zhhoee4c4y...@mail.gmail.com/ [3] https://github.com/megous/linux/commit/eb5f28fb58727f4a6546f211486aad0d19cdea3f Frank Oltmanns (1): drm/sun4i: tcon: Fix setting PLL rate when using DSI drivers/gpu/drm/sun4i/sun4i_tcon.c | 46 ++++++++++++++++++++---------- 1 file changed, 31 insertions(+), 15 deletions(-) -- 2.39.2
