[PATCH v3 3/6] drm/msm/dpu: Fix slice_last_group_size calculation

[Jessica Zhang]

Correct the math for slice_last_group_size so that it matches the
calculations downstream.

Changes in v3:
- Reworded slice_last_group_size calculation to
  `(dsc->slice_width + 2) % 3`

Fixes: c110cfd1753e ("drm/msm/disp/dpu1: Add support for DSC")
Signed-off-by: Jessica Zhang <quic_jessz...@quicinc.com>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
index b952f7d2b7f5..ff1c8f92fb20 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
@@ -56,9 +56,10 @@ static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc,
        if (is_cmd_mode)
                initial_lines += 1;
 
-       slice_last_group_size = 3 - (dsc->slice_width % 3);
+       slice_last_group_size = (dsc->slice_width + 2) % 3;
+
        data = (initial_lines << 20);
-       data |= ((slice_last_group_size - 1) << 18);
+       data |= (slice_last_group_size << 18);
        /* bpp is 6.4 format, 4 LSBs bits are for fractional part */
        data |= (dsc->bits_per_pixel << 8);
        data |= (dsc->block_pred_enable << 7);

-- 
2.40.0