On Wed, Jun 07, 2023 at 11:45:02AM +0200, Stanislaw Gruszka wrote:
> From: Andrzej Kacprowski <[email protected]>
>
> Wait for AON bit in HOST_SS_CPR_RST_CLR to return 0 before
> starting VPUIP power up sequence, otherwise the VPU device
> may sporadically fail to boot.
>
> An error in power up sequence is propagated to the runtime
> power management - the device will be in an error state
> until the VPU driver is reloaded.
>
> Fixes: 35b137630f08 ("accel/ivpu: Introduce a new DRM driver for Intel VPU")
> Cc: [email protected] # 6.3.x
> Signed-off-by: Andrzej Kacprowski <[email protected]>
> Reviewed-by: Krystian Pradzynski <[email protected]>
> Signed-off-by: Stanislaw Gruszka <[email protected]>
Applied to drm-misc-fixes
Thanks
Stanislaw
> ---
> drivers/accel/ivpu/ivpu_hw_mtl.c | 13 ++++++++++++-
> drivers/accel/ivpu/ivpu_hw_mtl_reg.h | 1 +
> 2 files changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/accel/ivpu/ivpu_hw_mtl.c
> b/drivers/accel/ivpu/ivpu_hw_mtl.c
> index 382ec127be8e..efae679d7b7a 100644
> --- a/drivers/accel/ivpu/ivpu_hw_mtl.c
> +++ b/drivers/accel/ivpu/ivpu_hw_mtl.c
> @@ -197,6 +197,11 @@ static void ivpu_pll_init_frequency_ratios(struct
> ivpu_device *vdev)
> hw->pll.pn_ratio = clamp_t(u8, fuse_pn_ratio, hw->pll.min_ratio,
> hw->pll.max_ratio);
> }
>
> +static int ivpu_hw_mtl_wait_for_vpuip_bar(struct ivpu_device *vdev)
> +{
> + return REGV_POLL_FLD(MTL_VPU_HOST_SS_CPR_RST_CLR, AON, 0, 100);
> +}
> +
> static int ivpu_pll_drive(struct ivpu_device *vdev, bool enable)
> {
> struct ivpu_hw_info *hw = vdev->hw;
> @@ -239,6 +244,12 @@ static int ivpu_pll_drive(struct ivpu_device *vdev, bool
> enable)
> ivpu_err(vdev, "Timed out waiting for PLL ready
> status\n");
> return ret;
> }
> +
> + ret = ivpu_hw_mtl_wait_for_vpuip_bar(vdev);
> + if (ret) {
> + ivpu_err(vdev, "Timed out waiting for VPUIP bar\n");
> + return ret;
> + }
> }
>
> return 0;
> @@ -256,7 +267,7 @@ static int ivpu_pll_disable(struct ivpu_device *vdev)
>
> static void ivpu_boot_host_ss_rst_clr_assert(struct ivpu_device *vdev)
> {
> - u32 val = REGV_RD32(MTL_VPU_HOST_SS_CPR_RST_CLR);
> + u32 val = 0;
>
> val = REG_SET_FLD(MTL_VPU_HOST_SS_CPR_RST_CLR, TOP_NOC, val);
> val = REG_SET_FLD(MTL_VPU_HOST_SS_CPR_RST_CLR, DSS_MAS, val);
> diff --git a/drivers/accel/ivpu/ivpu_hw_mtl_reg.h
> b/drivers/accel/ivpu/ivpu_hw_mtl_reg.h
> index d83ccfd9a871..593b8ff07417 100644
> --- a/drivers/accel/ivpu/ivpu_hw_mtl_reg.h
> +++ b/drivers/accel/ivpu/ivpu_hw_mtl_reg.h
> @@ -91,6 +91,7 @@
> #define MTL_VPU_HOST_SS_CPR_RST_SET_MSS_MAS_MASK
> BIT_MASK(11)
>
> #define MTL_VPU_HOST_SS_CPR_RST_CLR
> 0x00000098u
> +#define MTL_VPU_HOST_SS_CPR_RST_CLR_AON_MASK
> BIT_MASK(0)
> #define MTL_VPU_HOST_SS_CPR_RST_CLR_TOP_NOC_MASK
> BIT_MASK(1)
> #define MTL_VPU_HOST_SS_CPR_RST_CLR_DSS_MAS_MASK
> BIT_MASK(10)
> #define MTL_VPU_HOST_SS_CPR_RST_CLR_MSS_MAS_MASK
> BIT_MASK(11)
> --
> 2.25.1
>
