[PATCH] drm/i915/mtl: Update cache coherency setting for context structure

[Zhanjun Dong]

As context structure is shared memory for CPU/GPU, Wa_22016122933 is
needed for this memory block as well.

Signed-off-by: Zhanjun Dong <zhanjun.d...@intel.com>
CC: Fei Yang <fei.y...@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c 
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index a4ec20aaafe2..1b710102390b 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1092,8 +1092,15 @@ __lrc_alloc_state(struct intel_context *ce, struct 
intel_engine_cs *engine)
 
        obj = i915_gem_object_create_lmem(engine->i915, context_size,
                                          I915_BO_ALLOC_PM_VOLATILE);
-       if (IS_ERR(obj))
+       if (IS_ERR(obj)) {
                obj = i915_gem_object_create_shmem(engine->i915, context_size);
+               /*
+                * Wa_22016122933: For MTL the shared memory needs to be mapped
+                * as WC on CPU side and UC (PAT index 2) on GPU side
+                */
+               if (IS_METEORLAKE(engine->i915))
+                       i915_gem_object_set_cache_coherency(obj, 
I915_CACHE_NONE);
+       }
        if (IS_ERR(obj))
                return ERR_CAST(obj);
 
-- 
2.34.1