[PATCH v2 3/3] drm/i915/gt/pxp: User PXP contexts requires runalone bit in lrc

[Alan Previn]

On Meteorlake onwards, HW specs require that all user contexts that
run on render or compute engines and require PXP must enforce
run-alone bit in lrc. Add this enforcement for protected contexts.

Signed-off-by: Alan Previn <alan.previn.teres.ale...@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c 
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 957d0aeb0c02..2dfa49a04172 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -845,6 +845,16 @@ lrc_setup_indirect_ctx(u32 *regs,
                lrc_ring_indirect_offset_default(engine) << 6;
 }
 
+static bool ctx_needs_runalone(const struct intel_context *ce)
+{
+       if (GRAPHICS_VER_FULL(ce->engine->i915) >= IP_VER(12, 70) &&
+           ce->gem_context && ce->gem_context->uses_protected_content &&
+           (ce->engine->class == COMPUTE_CLASS || ce->engine->class == 
RENDER_CLASS))
+               return true;
+
+       return false;
+}
+
 static void init_common_regs(u32 * const regs,
                             const struct intel_context *ce,
                             const struct intel_engine_cs *engine,
@@ -860,6 +870,8 @@ static void init_common_regs(u32 * const regs,
        if (GRAPHICS_VER(engine->i915) < 11)
                ctl |= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT |
                                           CTX_CTRL_RS_CTX_ENABLE);
+       if (ctx_needs_runalone(ce))
+               ctl |= _MASKED_BIT_ENABLE(BIT(7));
        regs[CTX_CONTEXT_CONTROL] = ctl;
 
        regs[CTX_TIMESTAMP] = ce->stats.runtime.last;
-- 
2.39.0