[PATCH v3 8/8] drm/msm/dpu: move INTF tearing checks to dpu_encoder_phys_cmd_init

[Dmitry Baryshkov]

As the INTF is fixed at the encoder creation time, we can move the
check whether INTF supports tearchck to dpu_encoder_phys_cmd_init().
This function can return an error if INTF doesn't have required feature.
Performing this check in dpu_encoder_phys_cmd_tearcheck_config() is less
useful, as this function returns void.

Signed-off-by: Dmitry Baryshkov <dmitry.barysh...@linaro.org>
---
 .../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c  | 39 +++++++++++--------
 1 file changed, 23 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index d18236bd98e6..ca1296379c4d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -325,24 +325,21 @@ static void dpu_encoder_phys_cmd_tearcheck_config(
        unsigned long vsync_hz;
        struct dpu_kms *dpu_kms;
 
-       if (phys_enc->has_intf_te) {
-               if (!phys_enc->hw_intf ||
-                   !phys_enc->hw_intf->ops.enable_tearcheck) {
-                       DPU_DEBUG_CMDENC(cmd_enc, "tearcheck not supported\n");
-                       return;
-               }
-
-               DPU_DEBUG_CMDENC(cmd_enc, "");
-       } else {
-               if (!phys_enc->hw_pp ||
-                   !phys_enc->hw_pp->ops.enable_tearcheck) {
-                       DPU_DEBUG_CMDENC(cmd_enc, "tearcheck not supported\n");
-                       return;
-               }
-
-               DPU_DEBUG_CMDENC(cmd_enc, "pp %d\n", phys_enc->hw_pp->idx - 
PINGPONG_0);
+       /*
+        * TODO: if/when resource allocation is refactored, move this to a
+        * place where the driver can actually return an error.
+        */
+       if (!phys_enc->has_intf_te &&
+           (!phys_enc->hw_pp ||
+            !phys_enc->hw_pp->ops.enable_tearcheck)) {
+               DPU_DEBUG_CMDENC(cmd_enc, "tearcheck not supported\n");
+               return;
        }
 
+       DPU_DEBUG_CMDENC(cmd_enc, "intf %d pp %d\n",
+                        phys_enc->hw_intf ? phys_enc->hw_intf->idx - INTF_0 : 
-1,
+                        phys_enc->hw_pp ? phys_enc->hw_pp->idx - PINGPONG_0 : 
-1);
+
        mode = &phys_enc->cached_mode;
 
        dpu_kms = phys_enc->dpu_kms;
@@ -768,10 +765,20 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(
        phys_enc->intf_mode = INTF_MODE_CMD;
        cmd_enc->stream_sel = 0;
 
+       if (!phys_enc->hw_intf) {
+               DPU_ERROR_CMDENC(cmd_enc, "no INTF provided\n");
+               return ERR_PTR(-EINVAL);
+       }
+
        /* DPU before 5.0 use PINGPONG for TE handling */
        if (phys_enc->dpu_kms->catalog->mdss_ver->core_major_ver >= 5)
                phys_enc->has_intf_te = true;
 
+       if (phys_enc->has_intf_te && !phys_enc->hw_intf->ops.enable_tearcheck) {
+               DPU_ERROR_CMDENC(cmd_enc, "tearcheck not supported\n");
+               return ERR_PTR(-EINVAL);
+       }
+
        atomic_set(&cmd_enc->pending_vblank_cnt, 0);
        init_waitqueue_head(&cmd_enc->pending_vblank_wq);
 
-- 
2.39.2