Virtual wide planes give high amount of flexibility, but it is not
always enough:
In parallel multirect case only the half of the usual width is supported
for tiled formats. Thus the whole width of two tiled multirect
rectangles can not be greater than max_linewidth, which is not enough
for some platforms/compositors.
Another example is as simple as wide YUV plane. YUV planes can not use
multirect, so currently they are limited to max_linewidth too.
Now that the planes are fully virtualized, add support for allocating
two SSPP blocks to drive a single DRM plane. This fixes both mentioned
cases and allows all planes to go up to 2*max_linewidth (at the cost of
making some of the planes unavailable to the user).
Signed-off-by: Dmitry Baryshkov <dmitry.barysh...@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 170 ++++++++++++++++------
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 8 +
2 files changed, 130 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 2ac6e1074c62..9ffbcd91661a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -867,6 +867,28 @@ static int dpu_plane_atomic_check_nopipe(struct drm_plane
*plane,
return 0;
}
+static int dpu_plane_is_multirect_parallel_capable(struct dpu_sw_pipe *pipe,
+ struct dpu_sw_pipe_cfg
*pipe_cfg,
+ const struct dpu_format *fmt,
+ uint32_t max_linewidth)
+{
+ if (drm_rect_width(&pipe_cfg->src_rect) !=
drm_rect_width(&pipe_cfg->dst_rect) ||
+ drm_rect_height(&pipe_cfg->src_rect) !=
drm_rect_height(&pipe_cfg->dst_rect))
+ return false;
+
+ if (pipe_cfg->rotation & DRM_MODE_ROTATE_90)
+ return false;
+
+ if (DPU_FORMAT_IS_YUV(fmt))
+ return false;
+
+ if (DPU_FORMAT_IS_UBWC(fmt) &&
+ drm_rect_width(&pipe_cfg->src_rect) > max_linewidth / 2)
+ return false;
+
+ return true;
+}
+
static int dpu_plane_atomic_check_pipes(struct drm_plane *plane,
struct drm_atomic_state *state)
{
@@ -880,7 +902,6 @@ static int dpu_plane_atomic_check_pipes(struct drm_plane
*plane,
const struct dpu_format *fmt;
struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg;
- uint32_t max_linewidth;
uint32_t supported_rotations;
const struct dpu_sspp_cfg *pipe_hw_caps;
const struct dpu_sspp_sub_blks *sblk;
@@ -895,15 +916,8 @@ static int dpu_plane_atomic_check_pipes(struct drm_plane
*plane,
if (ret)
return ret;
- pipe->multirect_index = DPU_SSPP_RECT_SOLO;
- pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
- r_pipe->multirect_index = DPU_SSPP_RECT_SOLO;
- r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
-
fmt = to_dpu_format(msm_framebuffer_format(new_plane_state->fb));
- max_linewidth = pdpu->catalog->caps->max_linewidth;
-
supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0;
if (pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION))
@@ -918,40 +932,6 @@ static int dpu_plane_atomic_check_pipes(struct drm_plane
*plane,
return ret;
if (drm_rect_width(&r_pipe_cfg->src_rect) != 0) {
- /*
- * In parallel multirect case only the half of the usual width
- * is supported for tiled formats. If we are here, we know that
- * full width is more than max_linewidth, thus each rect is
- * wider than allowed.
- */
- if (DPU_FORMAT_IS_UBWC(fmt)) {
- DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT "
line:%u, tiled format\n",
- DRM_RECT_ARG(&pipe_cfg->src_rect),
max_linewidth);
- return -E2BIG;
- }
-
- if (drm_rect_width(&pipe_cfg->src_rect) !=
drm_rect_width(&pipe_cfg->dst_rect) ||
- drm_rect_height(&pipe_cfg->src_rect) !=
drm_rect_height(&pipe_cfg->dst_rect) ||
- (!test_bit(DPU_SSPP_SMART_DMA_V1,
&pipe->sspp->cap->features) &&
- !test_bit(DPU_SSPP_SMART_DMA_V2,
&pipe->sspp->cap->features)) ||
- pipe_cfg->rotation & DRM_MODE_ROTATE_90 ||
- DPU_FORMAT_IS_YUV(fmt)) {
- DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT "
line:%u, can't use split source\n",
- DRM_RECT_ARG(&pipe_cfg->src_rect),
max_linewidth);
- return -E2BIG;
- }
-
- /*
- * Use multirect for wide plane. We do not support dynamic
- * assignment of SSPPs, so we know the configuration.
- */
- pipe->multirect_index = DPU_SSPP_RECT_0;
- pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL;
-
- r_pipe->sspp = pipe->sspp;
- r_pipe->multirect_index = DPU_SSPP_RECT_1;
- r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL;
-
ret = dpu_plane_atomic_check_pipe(pdpu, r_pipe, r_pipe_cfg,
fmt);
if (ret)
return ret;
@@ -971,16 +951,16 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
struct dpu_sw_pipe *pipe = &pstate->pipe;
struct dpu_sw_pipe *r_pipe = &pstate->r_pipe;
+ struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
+ struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg;
const struct drm_crtc_state *crtc_state = NULL;
if (new_plane_state->crtc)
crtc_state = drm_atomic_get_new_crtc_state(state,
new_plane_state->crtc);
- if (pdpu->pipe != SSPP_NONE) {
- pipe->sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe);
- r_pipe->sspp = NULL;
- }
+ pipe->sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe);
+ r_pipe->sspp = NULL;
if (!pipe->sspp)
return -EINVAL;
@@ -992,6 +972,51 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
if (!new_plane_state->visible)
return 0;
+ pipe->multirect_index = DPU_SSPP_RECT_SOLO;
+ pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
+ r_pipe->multirect_index = DPU_SSPP_RECT_SOLO;
+ r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
+
+ if (drm_rect_width(&r_pipe_cfg->src_rect) != 0) {
+ uint32_t max_linewidth = dpu_kms->catalog->caps->max_linewidth;
+ const struct dpu_format *fmt;
+
+ fmt =
to_dpu_format(msm_framebuffer_format(new_plane_state->fb));
+
+ /*
+ * In parallel multirect case only the half of the usual width
+ * is supported for tiled formats. If we are here, we know that
+ * full width is more than max_linewidth, thus each rect is
+ * wider than allowed.
+ */
+ if (DPU_FORMAT_IS_UBWC(fmt)) {
+ DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT "
line:%u, tiled format\n",
+ DRM_RECT_ARG(&pipe_cfg->src_rect),
max_linewidth);
+ return -E2BIG;
+ }
+
+ r_pipe->sspp = pipe->sspp;
+
+ if (!dpu_plane_is_multirect_parallel_capable(pipe, pipe_cfg,
fmt, max_linewidth) ||
+ !dpu_plane_is_multirect_parallel_capable(r_pipe,
r_pipe_cfg, fmt, max_linewidth) ||
+ !(test_bit(DPU_SSPP_SMART_DMA_V1,
&pipe->sspp->cap->features) ||
+ test_bit(DPU_SSPP_SMART_DMA_V2,
&pipe->sspp->cap->features))) {
+ DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT "
line:%u, can't use split source\n",
+ DRM_RECT_ARG(&pipe_cfg->src_rect),
max_linewidth);
+ return -E2BIG;
+ }
+
+ /*
+ * Use multirect for wide plane. We do not support dynamic
+ * assignment of SSPPs, so we know the configuration.
+ */
+ pipe->multirect_index = DPU_SSPP_RECT_0;
+ pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL;
+
+ r_pipe->multirect_index = DPU_SSPP_RECT_1;
+ r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL;
+ }
+
return dpu_plane_atomic_check_pipes(plane, state);
}
@@ -1026,10 +1051,18 @@ static int dpu_plane_virtual_atomic_check(struct
drm_plane *plane,
format = to_dpu_format(msm_framebuffer_format(plane_state->fb));
- /* force resource reallocation if the format of FB has changed */
- if (pstate->saved_fmt != format) {
+ /* force resource reallocation if the format of FB or src/dst have
changed */
+ if (pstate->saved_fmt != format ||
+ pstate->saved_src_w != plane_state->src_w ||
+ pstate->saved_src_h != plane_state->src_h ||
+ pstate->saved_src_w != plane_state->src_w ||
+ pstate->saved_crtc_h != plane_state->crtc_h) {
crtc_state->planes_changed = true;
pstate->saved_fmt = format;
+ pstate->saved_src_w = plane_state->src_w;
+ pstate->saved_src_h = plane_state->src_h;
+ pstate->saved_crtc_w = plane_state->crtc_w;
+ pstate->saved_crtc_h = plane_state->crtc_h;
}
return 0;
@@ -1046,11 +1079,16 @@ static int dpu_plane_virtual_assign_resources(struct
drm_crtc *crtc,
struct dpu_plane_state *pstate;
struct dpu_sw_pipe *pipe;
struct dpu_sw_pipe *r_pipe;
+ struct dpu_sw_pipe_cfg *pipe_cfg;
+ struct dpu_sw_pipe_cfg *r_pipe_cfg;
const struct dpu_format *fmt;
+ uint32_t max_linewidth;
pstate = to_dpu_plane_state(plane_state);
pipe = &pstate->pipe;
r_pipe = &pstate->r_pipe;
+ pipe_cfg = &pstate->pipe_cfg;
+ r_pipe_cfg = &pstate->r_pipe_cfg;
pipe->sspp = NULL;
r_pipe->sspp = NULL;
@@ -1065,10 +1103,46 @@ static int dpu_plane_virtual_assign_resources(struct
drm_crtc *crtc,
reqs.rot90 = drm_rotation_90_or_270(plane_state->rotation);
+ max_linewidth = dpu_kms->catalog->caps->max_linewidth;
+
pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc,
&reqs);
if (!pipe->sspp)
return -ENODEV;
+ if (drm_rect_width(&r_pipe_cfg->src_rect) == 0) {
+ pipe->multirect_index = DPU_SSPP_RECT_SOLO;
+ pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
+
+ r_pipe->multirect_index = DPU_SSPP_RECT_SOLO;
+ r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
+
+ r_pipe->sspp = NULL;
+ } else {
+ if (dpu_plane_is_multirect_parallel_capable(pipe, pipe_cfg,
fmt, max_linewidth) &&
+ dpu_plane_is_multirect_parallel_capable(r_pipe, r_pipe_cfg,
fmt, max_linewidth) &&
+ (test_bit(DPU_SSPP_SMART_DMA_V1,
&pipe->sspp->cap->features) ||
+ test_bit(DPU_SSPP_SMART_DMA_V2,
&pipe->sspp->cap->features))) {
+ r_pipe->sspp = pipe->sspp;
+
+ pipe->multirect_index = DPU_SSPP_RECT_0;
+ pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL;
+
+ r_pipe->multirect_index = DPU_SSPP_RECT_1;
+ r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL;
+ } else {
+ /* multirect is not possible, use two SSPP blocks */
+ r_pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm,
global_state, crtc, &reqs);
+ if (!r_pipe->sspp)
+ return -ENODEV;
+
+ pipe->multirect_index = DPU_SSPP_RECT_SOLO;
+ pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
+
+ r_pipe->multirect_index = DPU_SSPP_RECT_SOLO;
+ r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
+ }
+ }
+
return dpu_plane_atomic_check_pipes(plane, state);
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
index 15f7d60d8b85..5522f9035d68 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
@@ -31,6 +31,10 @@
* @plane_clk: calculated clk per plane
* @needs_dirtyfb: whether attached CRTC needs pixel data explicitly flushed
* @saved_fmt: format used by the plane's FB, saved for for virtual plane
support
+ * @saved_src_w: cached value of plane's src_w, saved for for virtual plane
support
+ * @saved_src_h: cached value of plane's src_h, saved for for virtual plane
support
+ * @saved_crtc_w: cached value of plane's crtc_w, saved for for virtual plane
support
+ * @saved_crtc_h: cached value of plane's crtc_h, saved for for virtual plane
support
*/
struct dpu_plane_state {
struct drm_plane_state base;
@@ -49,6 +53,10 @@ struct dpu_plane_state {
bool needs_dirtyfb;
const struct dpu_format *saved_fmt;
+ uint32_t saved_src_w;
+ uint32_t saved_src_h;
+ uint32_t saved_crtc_w;
+ uint32_t saved_crtc_h;
};
#define to_dpu_plane_state(x) \
--
2.39.2
