[PATCH 01/14] accel/habanalabs: improve etf configuration

[Oded Gabbay]

From: Benjamin Dotan <bdo...@habana.ai>

coresight ETF blocks have different size. As a result, sync packets
need to be aligned based on fifo size.

Signed-off-by: Benjamin Dotan <bdo...@habana.ai>
Reviewed-by: Oded Gabbay <ogab...@kernel.org>
Signed-off-by: Oded Gabbay <ogab...@kernel.org>
---
 drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c 
b/drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c
index 32e0f1a85b35..14a855cdc96b 100644
--- a/drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c
+++ b/drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c
@@ -2125,10 +2125,17 @@ static int gaudi2_config_etf(struct hl_device *hdev, 
struct hl_debug_params *par
                if (!input)
                        return -EINVAL;
 
+               val = RREG32(base_reg + mmETF_RSZ_OFFSET) << 2;
+               if (val) {
+                       val = ffs(val);
+                       WREG32(base_reg + mmETF_PSCR_OFFSET, val);
+               } else {
+                       WREG32(base_reg + mmETF_PSCR_OFFSET, 0x10);
+               }
+
                WREG32(base_reg + mmETF_BUFWM_OFFSET, 0x3FFC);
                WREG32(base_reg + mmETF_MODE_OFFSET, input->sink_mode);
                WREG32(base_reg + mmETF_FFCR_OFFSET, 0x4001);
-               WREG32(base_reg + mmETF_PSCR_OFFSET, 0x10);
                WREG32(base_reg + mmETF_CTL_OFFSET, 1);
        } else {
                WREG32(base_reg + mmETF_BUFWM_OFFSET, 0);
-- 
2.34.1