Hi All, Gentle ping. It is reviewed by both Laurent and Geert.
Can it be applied to drm-misc-next, if everyone is happy with this patch? Cheers, Biju > From: Biju Das <biju.das...@bp.renesas.com> > Sent: Wednesday, September 6, 2023 10:44 AM > Subject: [PATCH] drm: renesas: rcar-du: rzg2l_mipi_dsi: Update the comment > in rzg2l_mipi_dsi_start_video() > > Add missing space in the comment in rzg2l_mipi_dsi_start_video(). > > Reported-by: Pavel Machek <pa...@denx.de> > Closes: > Signed-off-by: Biju Das <biju.das...@bp.renesas.com> > --- > This issue is noticed while backporting this driver to 6.1.y-cip [1]. > > [1] > --- > drivers/gpu/drm/renesas/rcar-du/rzg2l_mipi_dsi.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/renesas/rcar-du/rzg2l_mipi_dsi.c > b/drivers/gpu/drm/renesas/rcar-du/rzg2l_mipi_dsi.c > index 10febea473cd..9b5cfdd3e1c5 100644 > --- a/drivers/gpu/drm/renesas/rcar-du/rzg2l_mipi_dsi.c > +++ b/drivers/gpu/drm/renesas/rcar-du/rzg2l_mipi_dsi.c > @@ -479,7 +479,7 @@ static int rzg2l_mipi_dsi_start_video(struct > rzg2l_mipi_dsi *dsi) > u32 status; > int ret; > > - /* Configuration for Blanking sequence and start video input*/ > + /* Configuration for Blanking sequence and start video input */ > vich1set0r = VICH1SET0R_HFPNOLP | VICH1SET0R_HBPNOLP | > VICH1SET0R_HSANOLP | VICH1SET0R_VSTART; > rzg2l_mipi_dsi_link_write(dsi, VICH1SET0R, vich1set0r); > -- > 2.25.1
