[PATCH 2/5] clk: sunxi-ng: a64: Add constraints on PLL-MIPI's n/m ratio and parent rate

[Frank Oltmanns]

The Allwinner A64 manual lists the following constraints for the
PLL-MIPI clock:
 - M/N >= 3
 - (PLL_VIDEO0)/M >= 24MHz

Use these constraints.

Signed-off-by: Frank Oltmanns <fr...@oltmanns.dev>
---
 drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c 
b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
index 8951ffc14ff5..c034ac027d1c 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
@@ -176,6 +176,8 @@ static struct ccu_nkm pll_mipi_clk = {
        .n              = _SUNXI_CCU_MULT(8, 4),
        .k              = _SUNXI_CCU_MULT_MIN(4, 2, 2),
        .m              = _SUNXI_CCU_DIV(0, 4),
+       .max_mn_ratio   = 3,
+       .parent_wo_nk   = 24000000,
        .common         = {
                .reg            = 0x040,
                .hw.init        = CLK_HW_INIT("pll-mipi", "pll-video0",

-- 
2.43.0