On 2023-12-19 at 17:54:19 +0100, Jernej Škrabec <jernej.skra...@gmail.com> wrote: > Dne ponedeljek, 18. december 2023 ob 14:35:22 CET je Frank Oltmanns > napisal(a): >> The Allwinner A64 manual lists the following constraint for the >> PLL-VIDEO0 clock: 8 <= N/M <= 25 >> >> Use this constraint. >> >> Signed-off-by: Frank Oltmanns <fr...@oltmanns.dev> >> --- >> drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 8 ++++++-- >> 1 file changed, 6 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c >> b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c >> index c034ac027d1c..75d839da446c 100644 >> --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c >> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c >> @@ -68,7 +68,8 @@ static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, >> "pll-audio-base", >> BIT(28), /* lock */ >> CLK_SET_RATE_UNGATE); >> >> -static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_CLOSEST(pll_video0_clk, >> "pll-video0", >> +static >> SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_FEAT_NM_RATIO(pll_video0_clk, >> + "pll-video0", >> "osc24M", 0x010, >> 192000000, /* Minimum rate >> */ >> 1008000000, /* Maximum rate >> */
I just realized that adding the whole ratio limits for ccu_nm is superfluous as you could just as well express them in for of a minimum and maximum range: Since 8 <= N/M <= 25 and parent_rate = 24 MHz, therefore 192 MHz <= rate <= 600 MHz. These absolute limits are also listed in Allwinner's A64 manual. BUT, here the upper limit was raised to 1008 MHz: 5de39acaf34604bd04834f092479cf4dcc946dd "clk: sunxi-ng: a64: Add max. rate constraint to video PLL" With this upper limit the ratio limitation is effectively: 8 <= N/M <= 42 Icenowy Zheng (added to CC) had the reasonable explanation that this was used in the BSP kernel, so we should probably stick to that and ditch the two PLL-VIDEO0 related patches. What are your thoughts on that? >> @@ -80,7 +81,10 @@ static >> SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_CLOSEST(pll_video0_clk, "pll-vid >> 297000000, /* frac rate 1 >> */ >> BIT(31), /* gate */ >> BIT(28), /* lock */ >> - CLK_SET_RATE_UNGATE); >> + CLK_SET_RATE_UNGATE, >> + CCU_FEATURE_FRACTIONAL | >> + CCU_FEATURE_CLOSEST_RATE, > > Above flags are unrelated change, put them in new patch if needed. > > Best regards, > Jernej > >> + 8, 25); /* min/max nm >> ratio */ >> >> static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve", >> "osc24M", 0x018, >> >>
