From: Amjad Ouled-Ameur <amjad.ouled-am...@arm.com>
Each layer in the DPU has a 40-bit base address register, which indicates
start of frame buffer data for that layer. Komeda driver does not set
its DMA mask, which makes it 32-bit by default which does not use
the entire available possible supported by the DPU.
Update the DMA mask to align with DPU Architecture v1.0 spec.
Signed-off-by: Amjad Ouled-Ameur <amjad.ouled-am...@arm.com>
Signed-off-by: Faiz Abbas <faiz.ab...@arm.com>
---
drivers/gpu/drm/arm/display/komeda/komeda_drv.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_drv.c
b/drivers/gpu/drm/arm/display/komeda/komeda_drv.c
index cc57ea4e13ae..fea5a4818f33 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_drv.c
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_drv.c
@@ -59,6 +59,10 @@ static int komeda_platform_probe(struct platform_device
*pdev)
struct komeda_drv *mdrv;
int err;
+ err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
+ if (err)
+ return dev_err_probe(dev, err, "DMA mask error\n");
+
mdrv = devm_kzalloc(dev, sizeof(*mdrv), GFP_KERNEL);
if (!mdrv)
return -ENOMEM;
--
2.25.1
