On Tue, Nov 30, 2010 at 10:58 PM, april <aapril03 at gmail.com> wrote: > hi all: > > I have a question: > > If a BO in VRAM (WC) evict to SYS memory(may be cached), ?and user > process still can access it event it is in SYS memory (may be cached) > . > when this BO volidate to VRAM, ?It seems "ttm_bo_handle_move_mem" ?not > flush cache (If evict to SYS memory with cached). > > ?But flush cache is needed, If driver use DMA to handle BO > move(SYS->VRAM), should "ttm_bo_handle_move_mem" handle this? or > driver do it in "driver->move_notify" before "driver->move" called? > > Thanks
First not all cpu have instruction to explicitly flush cpu cache (at least i don't think so), second most GPU gart, through which DMA goes, can be CPU cache coherent, ie they will ask the CPU to flush its cache and this is what TTM expect. The setup is done at TTM gart registration where you say if your gart can be cache coherent or not (AGP for instance) if the gart is not cache coherent then ttm will change caching policy on bo page and this should trigger cache flush too. Cheers, Jerome
