> -----Original Message----- > From: Kaustabh Chakraborty <[email protected]> > Sent: Friday, September 20, 2024 12:11 AM > To: Inki Dae <[email protected]>; Seung-Woo Kim > <[email protected]>; Kyungmin Park <[email protected]>; David > Airlie <[email protected]>; Simona Vetter <[email protected]>; Krzysztof > Kozlowski <[email protected]>; Alim Akhtar <[email protected]>; > Maarten Lankhorst <[email protected]>; Maxime Ripard > <[email protected]>; Thomas Zimmermann <[email protected]>; Rob Herring > <[email protected]>; Conor Dooley <[email protected]> > Cc: [email protected]; [email protected]; > [email protected]; [email protected]; > [email protected]; Kaustabh Chakraborty <[email protected]> > Subject: [PATCH 3/6] drm/exynos: exynos7_drm_decon: fix ideal_clk by > converting it to Hz > > The clkdiv values are incorrect as ideal_clk is in kHz and the clock > rate of vclk is in Hz. Multiply 1000 to ideal_clk to bring it to Hz. > > Signed-off-by: Kaustabh Chakraborty <[email protected]> > --- > drivers/gpu/drm/exynos/exynos7_drm_decon.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/exynos/exynos7_drm_decon.c > b/drivers/gpu/drm/exynos/exynos7_drm_decon.c > index 2c4ee87ae6ec..4e4ced50ff15 100644 > --- a/drivers/gpu/drm/exynos/exynos7_drm_decon.c > +++ b/drivers/gpu/drm/exynos/exynos7_drm_decon.c > @@ -137,7 +137,7 @@ static void decon_ctx_remove(struct decon_context *ctx) > static u32 decon_calc_clkdiv(struct decon_context *ctx, > const struct drm_display_mode *mode) > { > - unsigned long ideal_clk = mode->clock; > + unsigned long ideal_clk = mode->clock * 1000; Right. ideal_clk should be fixed with Hz. Thanks, Inki Dae > u32 clkdiv; > > /* Find the clock divider value that gets us closest to ideal_clk > */ > > -- > 2.46.1
