On Sat, Oct 26, 2024 at 06:11:12AM +0200, Marek Vasut wrote: > The Pixel PLL is not very capable and may come up with wildly inaccurate > clock. Since DPI panels are often tolerant to slightly higher pixel clock > without being operated outside of specification, calculate two Pixel PLL > settings for DPI output, one for desired output pixel clock and one for > output pixel clock with 1% increase, and then pick the result which is > closer to the desired pixel clock and use it as the Pixel PLL settings.
The typical tolerance we've used is .5%, which is recommended by VESA in several specs. Differing from it for a good reason is ok I guess, but you need to document why. Maxime
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