[PATCH v3 05/10] clk: renesas: r8a779h0: Add display clocks

[Tomi Valkeinen]

From: Tomi Valkeinen <tomi.valkeinen+rene...@ideasonboard.com>

Add display related clocks for DU, DSI, FCPVD, and VSPD.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen+rene...@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+rene...@ideasonboard.com>
Tested-by: Geert Uytterhoeven <geert+rene...@glider.be>
---
 drivers/clk/renesas/r8a779h0-cpg-mssr.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c 
b/drivers/clk/renesas/r8a779h0-cpg-mssr.c
index e20c048bfa9b..dc37e987c0e6 100644
--- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c
@@ -179,6 +179,9 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] 
__initconst = {
        DEF_MOD("canfd0",       328,    R8A779H0_CLK_SASYNCPERD2),
        DEF_MOD("csi40",        331,    R8A779H0_CLK_CSI),
        DEF_MOD("csi41",        400,    R8A779H0_CLK_CSI),
+       DEF_MOD("dis0",         411,    R8A779H0_CLK_S0D3),
+       DEF_MOD("dsitxlink0",   415,    R8A779H0_CLK_DSIREF),
+       DEF_MOD("fcpvd0",       508,    R8A779H0_CLK_S0D3),
        DEF_MOD("hscif0",       514,    R8A779H0_CLK_SASYNCPERD1),
        DEF_MOD("hscif1",       515,    R8A779H0_CLK_SASYNCPERD1),
        DEF_MOD("hscif2",       516,    R8A779H0_CLK_SASYNCPERD1),
@@ -227,6 +230,7 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] 
__initconst = {
        DEF_MOD("vin15",        811,    R8A779H0_CLK_S0D4_VIO),
        DEF_MOD("vin16",        812,    R8A779H0_CLK_S0D4_VIO),
        DEF_MOD("vin17",        813,    R8A779H0_CLK_S0D4_VIO),
+       DEF_MOD("vspd0",        830,    R8A779H0_CLK_S0D1_VIO),
        DEF_MOD("wdt1:wdt0",    907,    R8A779H0_CLK_R),
        DEF_MOD("cmt0",         910,    R8A779H0_CLK_R),
        DEF_MOD("cmt1",         911,    R8A779H0_CLK_R),

-- 
2.43.0