> -----Original Message-----
> From: Dmitry Baryshkov <dmitry.barysh...@linaro.org>
> Sent: 2024年11月30日 16:30
> To: Sandor Yu <sandor...@nxp.com>
> Cc: andrzej.ha...@intel.com; neil.armstr...@linaro.org; Laurent Pinchart
> <laurent.pinch...@ideasonboard.com>; jo...@kwiboo.se;
> jernej.skra...@gmail.com; airl...@gmail.com; dan...@ffwll.ch;
> robh...@kernel.org; krzysztof.kozlowski...@linaro.org;
> shawn...@kernel.org; s.ha...@pengutronix.de; feste...@gmail.com;
> vk...@kernel.org; dri-devel@lists.freedesktop.org;
> devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> linux-ker...@vger.kernel.org; linux-...@lists.infradead.org;
> mrip...@kernel.org; ker...@pengutronix.de; dl-linux-imx
> <linux-...@nxp.com>; Oliver Brown <oliver.br...@nxp.com>;
> alexander.st...@ew.tq-group.com; s...@ravnborg.org
> Subject: Re: [EXT] Re: [PATCH v18 6/8] phy: freescale: Add DisplayPort/HDMI
> Combo-PHY driver for i.MX8MQ
>
> Caution: This is an external email. Please take care when clicking links or
> opening attachments. When in doubt, report the message using the 'Report
> this email' button
>
>
> On Tue, Nov 26, 2024 at 02:12:19PM +0000, Sandor Yu wrote:
> >
> > >
> > > On Tue, Nov 05, 2024 at 02:05:51PM +0000, Sandor Yu wrote:
> > > > >
> > > > > On Tue, Oct 29, 2024 at 02:02:14PM +0800, Sandor Yu wrote:
> > > > > > Add Cadence HDP-TX DisplayPort and HDMI PHY driver for
> i.MX8MQ.
> > > > > >
> > > > > > Cadence HDP-TX PHY could be put in either DP mode or HDMI mode
> > > > > > base on the configuration chosen.
> > > > > > DisplayPort or HDMI PHY mode is configured in the driver.
> > > > > >
> > > > > > Signed-off-by: Sandor Yu <sandor...@nxp.com>
> > > > > > Signed-off-by: Alexander Stein
> > > > > > <alexander.st...@ew.tq-group.com>
> > > > > > ---
> > > > > > v17->v18:
> > > > > > - fix build error as code rebase to latest kernel version.
> > > > > >
> > > > > > drivers/phy/freescale/Kconfig | 10 +
> > > > > > drivers/phy/freescale/Makefile | 1 +
> > > > > > drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c | 1337
> > > > > ++++++++++++++++++
> > > > > > 3 files changed, 1348 insertions(+) create mode 100644
> > > > > > drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c
> > > > > >
> > > > > > diff --git a/drivers/phy/freescale/Kconfig
> > > > > > b/drivers/phy/freescale/Kconfig index
> > > > > > dcd9acff6d01a..2b1210367b31c
> > > > > > 100644
> > > > > > --- a/drivers/phy/freescale/Kconfig
> > > > > > +++ b/drivers/phy/freescale/Kconfig
> > >
> > > [...]
> > >
> > > I'm sorry, my email client cut the email.
> > >
> > > > > > +static int cdns_hdptx_dp_configure(struct phy *phy,
> > > > > > + union phy_configure_opts
> > > *opts) {
> > > > > > + struct cdns_hdptx_phy *cdns_phy = phy_get_drvdata(phy);
> > > > > > +
> > > > > > + cdns_phy->dp.link_rate = opts->dp.link_rate;
> > > > > > + cdns_phy->dp.lanes = opts->dp.lanes;
> > > > >
> > > > > Shouldn't this be conditional on set_rate / set_lanes ?
> > > >
> > > > PHY do not support reconfigure link rate and lane count.
> > >
> > > So, you don't support reconfiguring the rate / count, but you still
> > > copy the new rate and lanes into your driver data. That sounds strange.
> >
> > The PHY will use link rate and lane count to configure its registers
>
> I'm not sure if I follow it. Do you mean that rate / count configuration is
> static?
In DP controller driver, rate and lane count are determined during link
training.
These two parameters are fixed in the DP PHY driver and cannot be modified.
Sandor
>
> --
> With best wishes
> Dmitry
