There is little point in rereading DP controller revision over and over
again. Read it once, after the first software reset.
Reviewed-by: Stephen Boyd <swb...@chromium.org>
Tested-by: Stephen Boyd <swb...@chromium.org> # sc7180-trogdor
Signed-off-by: Dmitry Baryshkov <dmitry.barysh...@linaro.org>
---
drivers/gpu/drm/msm/dp/dp_catalog.c | 29 ++++++++---------------------
drivers/gpu/drm/msm/dp/dp_catalog.h | 2 +-
2 files changed, 9 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c
b/drivers/gpu/drm/msm/dp/dp_catalog.c
index
4f80eceb6ae19f542110d7379007f57c2ac16a8a..23f9fcb75123a58b3a4b69d3dad0598135108eec
100644
--- a/drivers/gpu/drm/msm/dp/dp_catalog.c
+++ b/drivers/gpu/drm/msm/dp/dp_catalog.c
@@ -414,14 +414,13 @@ void msm_dp_catalog_ctrl_config_misc(struct
msm_dp_catalog *msm_dp_catalog,
void msm_dp_catalog_setup_peripheral_flush(struct msm_dp_catalog
*msm_dp_catalog)
{
- u32 mainlink_ctrl, hw_revision;
+ u32 mainlink_ctrl;
struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog,
struct msm_dp_catalog_private, msm_dp_catalog);
mainlink_ctrl = msm_dp_read_link(catalog, REG_DP_MAINLINK_CTRL);
- hw_revision = msm_dp_catalog_hw_revision(msm_dp_catalog);
- if (hw_revision >= DP_HW_VERSION_1_2)
+ if (msm_dp_catalog->hw_revision >= DP_HW_VERSION_1_2)
mainlink_ctrl |= DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE;
else
mainlink_ctrl |= DP_MAINLINK_FLUSH_MODE_UPDATE_SDP;
@@ -514,22 +513,6 @@ int msm_dp_catalog_ctrl_set_pattern_state_bit(struct
msm_dp_catalog *msm_dp_cata
return 0;
}
-/**
- * msm_dp_catalog_hw_revision() - retrieve DP hw revision
- *
- * @msm_dp_catalog: DP catalog structure
- *
- * Return: DP controller hw revision
- *
- */
-u32 msm_dp_catalog_hw_revision(const struct msm_dp_catalog *msm_dp_catalog)
-{
- const struct msm_dp_catalog_private *catalog =
container_of(msm_dp_catalog,
- struct msm_dp_catalog_private, msm_dp_catalog);
-
- return msm_dp_read_ahb(catalog, REG_DP_HW_VERSION);
-}
-
/**
* msm_dp_catalog_ctrl_reset() - reset DP controller
*
@@ -556,6 +539,9 @@ void msm_dp_catalog_ctrl_reset(struct msm_dp_catalog
*msm_dp_catalog)
sw_reset &= ~DP_SW_RESET;
msm_dp_write_ahb(catalog, REG_DP_SW_RESET, sw_reset);
+
+ if (!msm_dp_catalog->hw_revision)
+ msm_dp_catalog->hw_revision = msm_dp_read_ahb(catalog,
REG_DP_HW_VERSION);
}
bool msm_dp_catalog_ctrl_mainlink_ready(struct msm_dp_catalog *msm_dp_catalog)
@@ -895,9 +881,10 @@ static void msm_dp_catalog_panel_update_sdp(struct
msm_dp_catalog *msm_dp_catalo
u32 hw_revision;
catalog = container_of(msm_dp_catalog, struct msm_dp_catalog_private,
msm_dp_catalog);
+ hw_revision = msm_dp_catalog->hw_revision;
- hw_revision = msm_dp_catalog_hw_revision(msm_dp_catalog);
- if (hw_revision < DP_HW_VERSION_1_2 && hw_revision >=
DP_HW_VERSION_1_0) {
+ if (hw_revision < DP_HW_VERSION_1_2 &&
+ hw_revision >= DP_HW_VERSION_1_0) {
msm_dp_write_link(catalog, MMSS_DP_SDP_CFG3, 0x01);
msm_dp_write_link(catalog, MMSS_DP_SDP_CFG3, 0x00);
}
diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h
b/drivers/gpu/drm/msm/dp/dp_catalog.h
index
08bb42e91b779633875dbeb4130bc55a6571cfb1..379fa4fef9ceb63b20c4aec2fca1e09003dc738b
100644
--- a/drivers/gpu/drm/msm/dp/dp_catalog.h
+++ b/drivers/gpu/drm/msm/dp/dp_catalog.h
@@ -33,6 +33,7 @@
struct msm_dp_catalog {
bool wide_bus_en;
+ u32 hw_revision;
};
/* Debug module */
@@ -61,7 +62,6 @@ void msm_dp_catalog_ctrl_config_misc(struct msm_dp_catalog
*msm_dp_catalog, u32
void msm_dp_catalog_ctrl_config_msa(struct msm_dp_catalog *msm_dp_catalog, u32
rate,
u32 stream_rate_khz, bool is_ycbcr_420);
int msm_dp_catalog_ctrl_set_pattern_state_bit(struct msm_dp_catalog
*msm_dp_catalog, u32 pattern);
-u32 msm_dp_catalog_hw_revision(const struct msm_dp_catalog *msm_dp_catalog);
void msm_dp_catalog_ctrl_reset(struct msm_dp_catalog *msm_dp_catalog);
bool msm_dp_catalog_ctrl_mainlink_ready(struct msm_dp_catalog *msm_dp_catalog);
void msm_dp_catalog_ctrl_enable_irq(struct msm_dp_catalog *msm_dp_catalog,
bool enable);
--
2.39.5
