The IMG Rogue GPU requires three clocks: core, sys, and mem [1]. On the T-HEAD TH1520 SoC, the mem clock gate is marked as "Reserved" in the hardware manual (section 4.4.2.6.1) [2] and cannot be configured.
Add a new CCU_GATE_CLK_OPS macro that allows specifying custom clock operations. This enables us to use nop operations for the mem clock, preventing the driver from attempting to enable/disable this reserved clock gate. Link: https://lore.kernel.org/all/2fe3d93f-62ac-4439-ac17-d81137f64...@imgtec.com [1] Link: https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf [2] Signed-off-by: Michal Wilczynski <m.wilczyn...@samsung.com> --- drivers/clk/thead/clk-th1520-ap.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c index 57972589f120..ea96d007aecd 100644 --- a/drivers/clk/thead/clk-th1520-ap.c +++ b/drivers/clk/thead/clk-th1520-ap.c @@ -89,6 +89,21 @@ struct ccu_pll { } \ } +#define CCU_GATE_CLK_OPS(_clkid, _struct, _name, _parent, _reg, _gate, _flags, \ + _clk_ops) \ + struct ccu_gate _struct = { \ + .enable = _gate, \ + .common = { \ + .clkid = _clkid, \ + .cfg0 = _reg, \ + .hw.init = CLK_HW_INIT_PARENTS_DATA( \ + _name, \ + _parent, \ + &_clk_ops, \ + _flags), \ + } \ + } + static inline struct ccu_common *hw_to_ccu_common(struct clk_hw *hw) { return container_of(hw, struct ccu_common, hw); @@ -847,6 +862,11 @@ static CCU_GATE(CLK_SRAM1, sram1_clk, "sram1", axi_aclk_pd, 0x20c, BIT(3), 0); static CCU_GATE(CLK_SRAM2, sram2_clk, "sram2", axi_aclk_pd, 0x20c, BIT(2), 0); static CCU_GATE(CLK_SRAM3, sram3_clk, "sram3", axi_aclk_pd, 0x20c, BIT(1), 0); +static const struct clk_ops clk_nop_ops = {}; + +static CCU_GATE_CLK_OPS(CLK_GPU_MEM, gpu_mem_clk, "gpu-mem-clk", + video_pll_clk_pd, 0x0, BIT(2), 0, clk_nop_ops); + static CCU_GATE(CLK_AXI4_VO_ACLK, axi4_vo_aclk, "axi4-vo-aclk", video_pll_clk_pd, 0x0, BIT(0), 0); static CCU_GATE(CLK_GPU_CORE, gpu_core_clk, "gpu-core-clk", video_pll_clk_pd, @@ -1205,6 +1225,12 @@ static int th1520_clk_probe(struct platform_device *pdev) ret = devm_clk_hw_register(dev, &emmc_sdio_ref_clk.hw); if (ret) return ret; + } else if (plat_data == &th1520_vo_platdata) { + ret = devm_clk_hw_register(dev, &gpu_mem_clk.common.hw); + if (ret) + return ret; + gpu_mem_clk.common.map = map; + priv->hws[CLK_GPU_MEM] = &gpu_mem_clk.common.hw; } ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, priv); -- 2.34.1
