On Thu, 27 Mar 2025, Andi Shyti <andi.sh...@linux.intel.com> wrote: > From: Andi Shyti <andi.sh...@intel.com> > > Some GPUs, like DG2, can host more than one CCS engine. Some > workarounds or enablements need to happen only once for all the > engines in the GT—for example, on the engine with the lowest > instance. > > The FIRST_CCS() helper first checks if the engine is a Compute > engine, and then whether it's the one with the lowest instance. > > Signed-off-by: Andi Shyti <andi.sh...@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 54538b6f85df..5cb501393c4b 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -619,6 +619,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > #define CCS_MASK(gt) \ > ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS) > > +#define FIRST_CCS(e__) \ > + (CCS_MASK(e__->gt) && (__ffs(CCS_MASK(e__->gt)) == e__->instance)) > +
Could I persuade you to find a more specific header file for this, along with the CCS_MASK etc.? BR, Jani. > #define HAS_MEDIA_RATIO_MODE(i915) (INTEL_INFO(i915)->has_media_ratio_mode) > > /* -- Jani Nikula, Intel
