On 4/28/25 12:44 PM, Akhil P Oommen wrote:
> On 4/14/2025 4:31 PM, Konrad Dybcio wrote:
>> On 2/27/25 9:07 PM, Akhil P Oommen wrote:
>>> From: Jie Zhang <quic_ji...@quicinc.com>
>>>
>>> Add gpu and gmu nodes for qcs8300 chipset.
>>>
>>> Signed-off-by: Jie Zhang <quic_ji...@quicinc.com>
>>> Signed-off-by: Akhil P Oommen <quic_akhi...@quicinc.com>
>>> ---
>>
>> [...]
>>
>>> + gmu: gmu@3d6a000 {
>>> + compatible = "qcom,adreno-gmu-623.0", "qcom,adreno-gmu";
>>> + reg = <0x0 0x03d6a000 0x0 0x34000>,
>>
>> size = 0x26000 so that it doesn't leak into GPU_CC
>
> We dump GPUCC regs into snapshot!
Right, that's bad.. the dt heuristics are such that each region
is mapped by a single device that it belongs to, with some rare
exceptions..
Instead, the moderately dirty way would be to expose gpucc as
syscon & pass it to the GPU device, or the clean way would be
to implement an API within the clock framework that would dump
the relevant registers
Konrad
