On Wed, Apr 30, 2025 at 03:00:44PM +0200, Krzysztof Kozlowski wrote: > According to Hardware Programming Guide for DSI PHY, the retime buffer > resync should be done after PLL clock users (byte_clk and intf_byte_clk) > are enabled. Downstream also does it as part of configuring the PLL. > > Driver was only turning of the resync FIFO buffer, but never bringing it > on again. > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlow...@linaro.org> > > --- > > Changes in v5: > 1. New patch > --- > drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 4 ++++ > 1 file changed, 4 insertions(+) >
Reviewed-by: Dmitry Baryshkov <dmitry.barysh...@oss.qualcomm.com> -- With best wishes Dmitry
