On Thu, May 15, 2025 at 04:53:38PM +0530, Usyskin, Alexander wrote:
> > On Thu, Apr 24, 2025 at 04:25:27PM +0300, Alexander Usyskin wrote:
> > > In intel-dg, there is no access to the spi controller,
> > > the information is extracted from the descriptor region.
> >
> > ...
> >
> > > @@ -22,9 +24,199 @@ struct intel_dg_nvm {
> > > u8 id;
> > > u64 offset;
> > > u64 size;
> > > + unsigned int is_readable:1;
> > > + unsigned int is_writable:1;
> > > } regions[] __counted_by(nregions);
> > > };
> > >
> > > +#define NVM_TRIGGER_REG 0x00000000
> > > +#define NVM_VALSIG_REG 0x00000010
> > > +#define NVM_ADDRESS_REG 0x00000040
> > > +#define NVM_REGION_ID_REG 0x00000044
> > > +/*
> > > + * [15:0]-Erase size = 0x0010 4K 0x0080 32K 0x0100 64K
> > > + * [23:16]-Reserved
> > > + * [31:24]-Erase MEM RegionID
> > > + */
> > > +#define NVM_ERASE_REG 0x00000048
> > > +#define NVM_ACCESS_ERROR_REG 0x00000070
> > > +#define NVM_ADDRESS_ERROR_REG 0x00000074
> > > +
> > > +/* Flash Valid Signature */
> > > +#define NVM_FLVALSIG 0x0FF0A55A
> > > +
> > > +#define NVM_MAP_ADDR_MASK GENMASK(7, 0)
> > > +#define NVM_MAP_ADDR_SHIFT 0x00000004
> > > +
> > > +#define NVM_REGION_ID_DESCRIPTOR 0
> > > +/* Flash Region Base Address */
> > > +#define NVM_FRBA 0x40
> > > +/* Flash Region __n - Flash Descriptor Record */
> > > +#define NVM_FLREG(__n) (NVM_FRBA + ((__n) * 4))
> > > +/* Flash Map 1 Register */
> > > +#define NVM_FLMAP1_REG 0x18
> > > +#define NVM_FLMSTR4_OFFSET 0x00C
> > > +
> > > +#define NVM_ACCESS_ERROR_PCIE_MASK 0x7
> > > +
> > > +#define NVM_FREG_BASE_MASK GENMASK(15, 0)
> > > +#define NVM_FREG_ADDR_MASK GENMASK(31, 16)
> > > +#define NVM_FREG_ADDR_SHIFT 12
> > > +#define NVM_FREG_MIN_REGION_SIZE 0xFFF
> >
> > Should we move these to a header?
> They are used only in this file, not shared to anyone, why to put in header?
If we know we won't be further expanding/splitting, sure.
...
> > > +static bool idg_nvm_region_readable(u32 access_map, u8 region)
> > > +{
> > > + if (region < 12)
> >
> > Anything special about 12? Should it have a macro def somewhere?
> >
>
> The access bits are separated for first 12 regions and last 4.
> My feeling that making below numbers #define will make
> code less readable.
Then perhaps a small comment would be useful.
> > > + return access_map & BIT(region + 8); /* [19:8] */
> > > + else
> > > + return access_map & BIT(region - 12); /* [3:0] */
> > > +}
> > > +
> > > +static bool idg_nvm_region_writable(u32 access_map, u8 region)
> > > +{
> > > + if (region < 12)
Ditto.
> > > + return access_map & BIT(region + 20); /* [31:20] */
> > > + else
> > > + return access_map & BIT(region - 8); /* [7:4] */
> > > +}
Raag
