On Sat, May 17, 2025 at 07:32:42PM +0200, Konrad Dybcio wrote: > From: Konrad Dybcio <konrad.dyb...@oss.qualcomm.com> > > ubwc_swizzle is a bitmask. Check for a bit to make it more obvious. > > Signed-off-by: Konrad Dybcio <konrad.dyb...@oss.qualcomm.com> > --- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > index > 154346591365f3f89d467674952abb2f067e7ce3..a20b57e964d31adb22f0b79a5178b45f0f5ec5d5 > 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > @@ -668,12 +668,12 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) > */ > BUG_ON(adreno_gpu->ubwc_config.highest_bank_bit < 13); > u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit - 13; > + u32 level2_swizzling_dis = !(cfg->ubwc_swizzle & BIT(1));
Nit: UBWC_SWIZZLE_ENABLE_LVL2 ? Reviewed-by: Dmitry Baryshkov <dmitry.barysh...@oss.qualcomm.com> > bool ubwc_mode = qcom_ubwc_get_ubwc_mode(cfg); > bool amsbc = cfg->ubwc_enc_version >= UBWC_3_0; > u8 uavflagprd_inv = 0; > u32 hbb_hi = hbb >> 2; > u32 hbb_lo = hbb & 3; > - u32 level2_swizzling_dis = !(adreno_gpu->ubwc_config.ubwc_swizzle & 2); > > if (adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu)) > uavflagprd_inv = 2; > > -- > 2.49.0 > -- With best wishes Dmitry
