Hi Tomeu,
Am Dienstag, dem 20.05.2025 um 12:27 +0200 schrieb Tomeu Vizoso:
> The NPU cores have their own access to the memory bus, and this isn't
> cache coherent with the CPUs.
>
> Add IOCTLs so userspace can mark when the caches need to be flushed, and
> also when a writer job needs to be waited for before the buffer can be
> accessed from the CPU.
>
> Initially based on the same IOCTLs from the Etnaviv driver.
>
> v2:
> - Don't break UABI by reordering the IOCTL IDs (Jeff Hugo)
>
> v3:
> - Check that padding fields in IOCTLs are zero (Jeff Hugo)
>
> Signed-off-by: Tomeu Vizoso <to...@tomeuvizoso.net>
> ---
> drivers/accel/rocket/rocket_drv.c | 2 +
> drivers/accel/rocket/rocket_gem.c | 80
> +++++++++++++++++++++++++++++++++++++++
> drivers/accel/rocket/rocket_gem.h | 5 +++
> include/uapi/drm/rocket_accel.h | 37 ++++++++++++++++++
> 4 files changed, 124 insertions(+)
>
> diff --git a/drivers/accel/rocket/rocket_drv.c
> b/drivers/accel/rocket/rocket_drv.c
> index
> fef9b93372d3f65c41c1ac35a9bfa0c01ee721a5..c06e66939e6c39909fe08bef3c4f301b07bf8fbf
> 100644
> --- a/drivers/accel/rocket/rocket_drv.c
> +++ b/drivers/accel/rocket/rocket_drv.c
> @@ -59,6 +59,8 @@ static const struct drm_ioctl_desc
> rocket_drm_driver_ioctls[] = {
>
> ROCKET_IOCTL(CREATE_BO, create_bo),
> ROCKET_IOCTL(SUBMIT, submit),
> + ROCKET_IOCTL(PREP_BO, prep_bo),
> + ROCKET_IOCTL(FINI_BO, fini_bo),
> };
>
> DEFINE_DRM_ACCEL_FOPS(rocket_accel_driver_fops);
> diff --git a/drivers/accel/rocket/rocket_gem.c
> b/drivers/accel/rocket/rocket_gem.c
> index
> 8a8a7185daac4740081293aae6945c9b2bbeb2dd..cdc5238a93fa5978129dc1ac8ec8de955160dc18
> 100644
> --- a/drivers/accel/rocket/rocket_gem.c
> +++ b/drivers/accel/rocket/rocket_gem.c
> @@ -129,3 +129,83 @@ int rocket_ioctl_create_bo(struct drm_device *dev, void
> *data, struct drm_file *
>
> return ret;
> }
> +
> +static inline enum dma_data_direction rocket_op_to_dma_dir(u32 op)
> +{
> + if (op & ROCKET_PREP_READ)
> + return DMA_FROM_DEVICE;
> + else if (op & ROCKET_PREP_WRITE)
> + return DMA_TO_DEVICE;
> + else
> + return DMA_BIDIRECTIONAL;
> +}
This has copied over the bug fixed in etnaviv commit 58979ad6330a
("drm/etnaviv: fix DMA direction handling for cached RW buffers")
Regards,
Lucas
