[PATCH v3 2/2] drm: renesas: rz-du: Set DCS maximum return packet size

[Hugo Villeneuve]

From: Hugo Villeneuve <hvillene...@dimonoff.com>

The default value of 1 will result in long read commands payload not being
saved to memory.

Fix by setting this value to the DMA buffer size.

Cc: Biju Das <biju.das...@bp.renesas.com>
Cc: Chris Brandt <chris.bra...@renesas.com>
Signed-off-by: Hugo Villeneuve <hvillene...@dimonoff.com>
---
 drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c      | 10 ++++++++++
 drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h |  4 ++++
 2 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c 
b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
index a048d473db00b..745aae63af9d8 100644
--- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
+++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
@@ -549,6 +549,7 @@ static void rzg2l_mipi_dsi_atomic_enable(struct drm_bridge 
*bridge,
        const struct drm_display_mode *mode;
        struct drm_connector *connector;
        struct drm_crtc *crtc;
+       u32 value;
        int ret;
 
        connector = drm_atomic_get_new_connector_for_encoder(state, 
bridge->encoder);
@@ -561,6 +562,15 @@ static void rzg2l_mipi_dsi_atomic_enable(struct drm_bridge 
*bridge,
 
        rzg2l_mipi_dsi_set_display_timing(dsi, mode);
 
+       /*
+        * The default value of 1 will result in long read commands payload
+        * not being saved to memory. Set to the DMA buffer size.
+        */
+       value = rzg2l_mipi_dsi_link_read(dsi, DSISETR);
+       value &= ~DSISETR_MRPSZ;
+       value |= FIELD_PREP(DSISETR_MRPSZ, RZG2L_DCS_BUF_SIZE);
+       rzg2l_mipi_dsi_link_write(dsi, DSISETR, value);
+
        ret = rzg2l_mipi_dsi_start_hs_clock(dsi);
        if (ret < 0)
                goto err_stop;
diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h 
b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h
index 0e432b04188d0..26d8a37ee6351 100644
--- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h
+++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h
@@ -81,6 +81,10 @@
 #define RSTSR_SWRSTLP                  (1 << 1)
 #define RSTSR_SWRSTHS                  (1 << 0)
 
+/* DSI Set Register */
+#define DSISETR                                0x120
+#define DSISETR_MRPSZ                  GENMASK(15, 0)
+
 /* Rx Result Save Slot 0 Register */
 #define RXRSS0R                                0x240
 #define RXRSS0R_RXPKTDFAIL             BIT(28)
-- 
2.39.5