Hi Michael, Tomi,
On 27/05/25 18:03, Tomi Valkeinen wrote:
Hi Michael (and Aradhya, Devarsh),
On 27/05/2025 12:13, Michael Walle wrote:
Hi Tomi,
While testing Aardhya's OLDI support patches [1], I've noticed that
the resulting LVDS clock is wrong if this patch is applied.
In practice, with the current K3 SoCs, the display PLL is capable of
producing very exact clocks, so most likely the rounded rate is the same
as the original one.
Yes, display PLL is flexible and device manager should set exact
frequency. Please note that there was a bug in device manager in earlier
releases which would prevent setting it to exact clocks. You should try
with latest SDK release firmware binaries (11.0...(10.1 should also work
though)) if seeing any misbehaviour in that regard.
This is now what I'm seeing. Most SoCs have that fixed clock thingy
for (some?) VPs, e.g. [2]. And clk_round_rate() will return the
fixed clock rate for this clock, which will then result in an LVDS
clock which is way off.
I'm testing on an AM67A (J722S) and I've backported some of the
patches as well as dtsi fragmets from downstream. Thus, it might be
as well the case that the fixed-factor-clock node is wrong here.
OTOH other K3 SoCs do this in mainline as well.
Thanks for findings this (It's not a fixed clock, but a (fixed)
divider). I can reproduce on my AM62 SK's OLDI output.
I didn't see AM625 TRM explaining the DSS + OLDI clocking. I remember it
was a bit "interesting". Afaics from testing, the VP clock is derived
from the OLDI serial clock divided by 7. To change the VP clock, we need
to set the OLDI clock's rate. But the code we have at the moment is
using clk_round_rate/set_rate to the VP clock.
This is correct. The pixel clock is derived as OLDI clock/7 when OLDI is
enabled.
And we get the crtc atomic_check called before setting the OLDI clock
rate, so it doesn't even work by luck (i.e. if the OLDI clock was set
earlier, the VP clock would already have the right rate, and it would
seem that everything is ok). In the atomic_check we see the OLDI bypass
clock (25 MHz), which results in 3571428 Hz VP clock.
And with this patch, the code then decides that 3571428 Hz is what the
HW can do, and uses it as the pixel clock.
Aradhya, Devarsh, do you remember how the clocking goes here? Or if it's
in the TRM, please point me to it...
I think what you described is correct, if any specific questions I can
help check. But any misbehaviour you are seeing w.r.t clock setting
(i.e. what driver is trying to set versus what actually is getting set)
then please dump the dss clock tree along with relevant details of test
done:
k3conf dump clock <display_device_id>
You can get the device ID via TISCI Doc [1]
[1]:
https://downloads.ti.com/tisci/esd/latest/5_soc_doc/am62x/clocks.html#clock-for-am62x-device
Regards
Devarsh
