Hi Rob, [adding Kever to CC]
On Wed, May 28, 2025 at 3:41 PM Rob Herring <r...@kernel.org> wrote: > > On Tue, May 20, 2025 at 5:27 AM Tomeu Vizoso <to...@tomeuvizoso.net> wrote: > > > > Add the bindings for the Neural Processing Unit IP from Rockchip. > > > > v2: > > - Adapt to new node structure (one node per core, each with its own > > IOMMU) > > - Several misc. fixes from Sebastian Reichel > > > > v3: > > - Split register block in its constituent subblocks, and only require > > the ones that the kernel would ever use (Nicolas Frattaroli) > > - Group supplies (Rob Herring) > > - Explain the way in which the top core is special (Rob Herring) > > > > v4: > > - Change required node name to npu@ (Rob Herring and Krzysztof Kozlowski) > > - Remove unneeded items: (Krzysztof Kozlowski) > > - Fix use of minItems/maxItems (Krzysztof Kozlowski) > > - Add reg-names to list of required properties (Krzysztof Kozlowski) > > - Fix example (Krzysztof Kozlowski) > > > > v5: > > - Rename file to rockchip,rk3588-rknn-core.yaml (Krzysztof Kozlowski) > > - Streamline compatible property (Krzysztof Kozlowski) > > > > Signed-off-by: Sebastian Reichel <sebastian.reic...@collabora.com> > > Signed-off-by: Tomeu Vizoso <to...@tomeuvizoso.net> > > --- > > .../bindings/npu/rockchip,rk3588-rknn-core.yaml | 147 > > +++++++++++++++++++++ > > 1 file changed, 147 insertions(+) > > > > diff --git > > a/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml > > b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml > > new file mode 100644 > > index > > 0000000000000000000000000000000000000000..9eb426367afcbc03c387d43c4b8250cdd1b9ee86 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml > > @@ -0,0 +1,147 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/npu/rockchip,rk3588-rknn-core.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Neural Processing Unit IP from Rockchip > > + > > +maintainers: > > + - Tomeu Vizoso <to...@tomeuvizoso.net> > > + > > +description: > > + Rockchip IP for accelerating inference of neural networks, based on > > NVIDIA's > > + open source NVDLA IP. > > + > > + There is to be a node per each core in the NPU. In Rockchip's design > > there > > + will be one core that is special and needs to be powered on before any > > of the > > + other cores can be used. This special core is called the top core and > > should > > + have the compatible string that corresponds to top cores. > > Is this really a distinction in the h/w? If you change which core is > the top one in the DT, does it still work? > > > + > > +properties: > > + $nodename: > > + pattern: '^npu@[a-f0-9]+$' > > + > > + compatible: > > + enum: > > + - rockchip,rk3588-rknn-core-top > > + - rockchip,rk3588-rknn-core > > + > > + reg: > > + maxItems: 3 > > + > > + reg-names: > > + items: > > + - const: pc > > + - const: cna > > + - const: core > > + > > + clocks: > > + minItems: 2 > > + maxItems: 4 > > + > > + clock-names: > > + items: > > + - const: aclk > > + - const: hclk > > + - const: npu > > + - const: pclk > > + minItems: 2 > > It is odd that the non-top cores only have bus clocks and no module > clock. I'm not sure I get what you mean by module clock, but the TRM says this: "36.5.2 Clock and Reset 1.5.2.1 Clock Domains RKNN has two clock domains, one is AHB clock, the other is AXI clock. AHB clock, which is the clock for AHB interface, while AXI clock, which is the clock for AXI interface. AXI clock also used for core clock for every Calculate Core and Control Core. Clock frequency can be controlled by CRU, please refer to the relevant sections. Automatic localized clock gating is employed throughout the design in order to minimize the dynamic power consumption. Almost all of the flip-flops are clock gated in the design. Block level clock gating also implemented in every separate block. If a block and the interface to the block are both idle, then the clock of that block will be gated automatically. This feature can be disabled by software." So maybe the AXI (aclk?) clock is being used as what you called the module clock? > But based on the clock names, I'm guessing the aclk/hclk are > not shared, but the npu and pclk are shared. Since you make the top > core probe first, then it will enable the shared clocks and the > non-top cores don't have to worry about them. If so, that is wrong as > it is letting the software design define the bindings. I don't really know what the pclk and npu clk are needed for, but in the TRM I'm seeing references to the pclk being related to the core 0 (TOP): pclk_nputop_root_sel pclk_nputop_biu_en Couldn't find similar references to the "npu" clock though. Cheers, Tomeu
