The R-Car DSI host is capable of operating in 1..4 DSI lane mode.
Remove hard-coded 4-lane configuration from PPI register settings
and instead configure the PPI lane count according to lane count
information already obtained by this driver instance.
Signed-off-by: Marek Vasut <marek.vasut+rene...@mailbox.org>
---
Cc: David Airlie <airl...@gmail.com>
Cc: Geert Uytterhoeven <geert+rene...@glider.be>
Cc: Kieran Bingham <kieran.bingham+rene...@ideasonboard.com>
Cc: Laurent Pinchart <laurent.pinchart+rene...@ideasonboard.com>
Cc: Maarten Lankhorst <maarten.lankho...@linux.intel.com>
Cc: Magnus Damm <magnus.d...@gmail.com>
Cc: Maxime Ripard <mrip...@kernel.org>
Cc: Simona Vetter <sim...@ffwll.ch>
Cc: Thomas Zimmermann <tzimmerm...@suse.de>
Cc: Tomi Valkeinen <tomi.valkeinen+rene...@ideasonboard.com>
Cc: dri-devel@lists.freedesktop.org
Cc: linux-renesas-...@vger.kernel.org
---
drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c | 2 +-
drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h | 5 +----
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c
b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c
index 7ab8be46c7f6..373bd0040a46 100644
--- a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c
+++ b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c
@@ -576,7 +576,7 @@ static int rcar_mipi_dsi_startup(struct rcar_mipi_dsi *dsi,
udelay(10);
rcar_mipi_dsi_clr(dsi, CLOCKSET1, CLOCKSET1_UPDATEPLL);
- ppisetr = PPISETR_DLEN_3 | PPISETR_CLEN;
+ ppisetr = ((BIT(dsi->lanes) - 1) & PPISETR_DLEN_MASK) | PPISETR_CLEN;
rcar_mipi_dsi_write(dsi, PPISETR, ppisetr);
rcar_mipi_dsi_set(dsi, PHYSETUP, PHYSETUP_SHUTDOWNZ);
diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h
b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h
index b3e57217ae63..cefa7e92b5b8 100644
--- a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h
+++ b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h
@@ -80,10 +80,7 @@
* PHY-Protocol Interface (PPI) Registers
*/
#define PPISETR 0x700
-#define PPISETR_DLEN_0 (0x1 << 0)
-#define PPISETR_DLEN_1 (0x3 << 0)
-#define PPISETR_DLEN_2 (0x7 << 0)
-#define PPISETR_DLEN_3 (0xf << 0)
+#define PPISETR_DLEN_MASK (0xf << 0)
#define PPISETR_CLEN BIT(8)
#define PPICLCR 0x710
--
2.47.2
