From: Abhinav Kumar <quic_abhin...@quicinc.com>
Use msm_dp_get_mst_intf_id() to get the intf id for the DP MST
controller as the intf_id is unique for each MST stream of each
DP controller.
Signed-off-by: Abhinav Kumar <quic_abhin...@quicinc.com>
Signed-off-by: Yongxing Mou <quic_yong...@quicinc.com>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 21 ++++++++++----
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 43 +++++++++++++++++++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 2 +-
3 files changed, 60 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index
7020098360e474ee149824a488d912a7ad8ed06a..75cc2d475440fcdc941aa9eb19e78a87e83b5f5f
100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -2611,11 +2611,13 @@ uint32_t dpu_encoder_get_clones(struct drm_encoder
*drm_enc)
static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc,
struct dpu_kms *dpu_kms,
- struct msm_display_info *disp_info)
+ struct msm_display_info *disp_info,
+ int drm_enc_mode)
{
int ret = 0;
int i = 0;
struct dpu_enc_phys_init_params phys_params;
+ u32 intf_id;
if (!dpu_enc) {
DPU_ERROR("invalid arg(s), enc %d\n", dpu_enc != NULL);
@@ -2658,9 +2660,18 @@ static int dpu_encoder_setup_display(struct
dpu_encoder_virt *dpu_enc,
DPU_DEBUG("h_tile_instance %d = %d, split_role %d\n",
i, controller_id, phys_params.split_role);
- phys_params.hw_intf = dpu_encoder_get_intf(dpu_kms->catalog,
&dpu_kms->rm,
- disp_info->intf_type,
- controller_id);
+ if (drm_enc_mode == DRM_MODE_ENCODER_DPMST) {
+ intf_id = dpu_kms_get_mst_intf_id(dpu_kms,
controller_id,
+
disp_info->stream_id);
+ DPU_DEBUG("intf_id %d for disp_info->stream_id = %d\n",
intf_id,
+ disp_info->stream_id);
+ phys_params.hw_intf = dpu_rm_get_intf(&dpu_kms->rm,
intf_id);
+
+ } else {
+ phys_params.hw_intf =
dpu_encoder_get_intf(dpu_kms->catalog, &dpu_kms->rm,
+
disp_info->intf_type,
+
controller_id);
+ }
if (disp_info->intf_type == INTF_WB && controller_id < WB_MAX)
phys_params.hw_wb = dpu_rm_get_wb(&dpu_kms->rm,
controller_id);
@@ -2760,7 +2771,7 @@ struct drm_encoder *dpu_encoder_init(struct drm_device
*dev,
mutex_init(&dpu_enc->enc_lock);
mutex_init(&dpu_enc->rc_lock);
- ret = dpu_encoder_setup_display(dpu_enc, dpu_kms, disp_info);
+ ret = dpu_encoder_setup_display(dpu_enc, dpu_kms, disp_info,
drm_enc_mode);
if (ret) {
DPU_ERROR("failed to setup encoder\n");
return ERR_PTR(-ENOMEM);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index
e030476dc4c69448886c29bcfe8ff3105949b129..f82dcf7c6dd31f078bbe4afe55d4667a4867f0b7
100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -574,6 +574,49 @@ static int dpu_kms_dsi_set_te_source(struct
msm_display_info *info,
return -EINVAL;
}
+u32 dpu_kms_get_mst_intf_id(struct dpu_kms *dpu_kms, int controller_id, int
stream_id)
+{
+ const struct dpu_mdss_cfg *catalog = dpu_kms->catalog;
+ int i;
+ int cnt = 0;
+ u32 intf_id = INTF_0;
+
+ /* The intf order in dpu_intf_cfg matches the mapping in the DP HPG.
+ * DPU_8_4_0 - DP Controller intf to stream Mapping
+ *
+ * +-------------+----------+----------+----------+----------+
+ * | stream_id | 0 | 1 | 2 | 3 |
+ * +-------------+----------+----------+----------+----------+
+ * | DP0 | INTF_0 | INTF_3 | INTF_6 | INTF_7 |
+ * | DP1 | INTF_4 | INTF_8 | | |
+ * +-------------+----------+----------+----------+----------+
+ *
+ * DPU_9_2_0 - DP Controller intf to stream Mapping
+ *
+ * +-------------+----------+----------+
+ * | Controller | 0 | 1 |
+ * +-------------+----------+----------+
+ * | DP0 | INTF_0 | INTF_3 |
+ * | DP1 | INTF_4 | INTF_8 |
+ * | DP2 | INTF_6 | INTF_7 |
+ * +-------------+----------+----------+
+ */
+ for (i = 0; i < catalog->intf_count; i++) {
+ const struct dpu_intf_cfg *intf = &catalog->intf[i];
+
+ if (intf->type == INTF_DP && controller_id ==
intf->controller_id) {
+ if (cnt == stream_id) {
+ intf_id = intf->id;
+ break;
+ }
+
+ cnt++;
+ }
+ }
+
+ return intf_id;
+}
+
static int _dpu_kms_initialize_dsi(struct drm_device *dev,
struct msm_drm_private *priv,
struct dpu_kms *dpu_kms)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
index
a57ec2ec106083e8f93578e4307e8b13ae549c08..388cd8f84fd579ce30a69989be5ac116bb727878
100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
@@ -168,5 +168,5 @@ int dpu_enable_vblank(struct msm_kms *kms, struct drm_crtc
*crtc);
void dpu_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
unsigned long dpu_kms_get_clk_rate(struct dpu_kms *dpu_kms, char *clock_name);
-
+u32 dpu_kms_get_mst_intf_id(struct dpu_kms *dpu_kms, int controller_id, int
stream_id);
#endif /* __dpu_kms_H__ */
--
2.34.1
