On 18/06/25 13:28, Jayesh Choudhary wrote:
TIDSS hardware by itself does not have variable max_pclk for each VP. Each VP supports a fixed maximum pixel clock. K2 devices and AM62* devices uses "ultra-light" version where each VP supports a max of 300MHz whereas J7* devices uses TIDSS where all VP can support a max pclk of 600MHz. The limitation that has been modeled till now comes from the clock (PLL can only be programmed to a particular max value). Due to this we end up using different compatible for each SoC when the clocking architecture changes for VPs, even when the hardware is essentially the same. max_pclk cannot be entirely removed since the display controller should tell if a particular mode clock can be supported or not in crtc's "mode_valid()" call. So remove "max_pclk_khz" from the static display feat and add it to "tidss_device" structure which would be modified in runtime. In mode_valid() call, check if a best frequency match for mode clock can be found or not using "clk_round_rate()". Based on that, propagate "max_pclk" and check max_clk again only if the requested mode clock is greater than saved value. (As the preferred display mode is usually the max resolution, driver ends up checking the maximum clock the first time itself which is used in subsequent checks) Since TIDSS display controller provides clock tolerance of 5%, we use this while checking the max_pclk. Also, move up "dispc_pclk_diff()" before it is called. This will make the existing compatibles reusable. Signed-off-by: Jayesh Choudhary <[email protected]> --- Test log on TI's J784S4 SoC with a couple of downstream patches to integrate DSI support on one of the video ports: <https://gist.github.com/Jayesh2000/ad4ab87028740efa60e5eb83fb892097>
Hello All, Just noticed that the downstream patches that I used for DSI for testing were applied before this patch in my tree due to which this patch does not apply cleanly on the linux-next tree. Apologies for that. I am rolling v2 ASAP. Jayesh
From the logs, we can see that for CLK ID 218 (DSS), we do not have to call sci_clk_determine_rate() multiple times. So there is very little overhead of this call even with multiple mode_valid() called during display run. From weston-simple-egl application, I have seen that there is no frame drop or performance impact. Once this patch gets in, I will send patches for AM62P and J722S DSS support. drivers/gpu/drm/tidss/tidss_dispc.c | 76 ++++++++++++----------------- drivers/gpu/drm/tidss/tidss_dispc.h | 1 - drivers/gpu/drm/tidss/tidss_drv.h | 2 + 3 files changed, 34 insertions(+), 45 deletions(-)
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