The kernel's `Delta` type was not available when the `wait_on` function
was introduced. Now that it is, switch to it as it is more compact than
`Duration` and cannot panic.
Signed-off-by: Alexandre Courbot <acour...@nvidia.com>
---
drivers/gpu/nova-core/falcon.rs | 12 ++++++------
drivers/gpu/nova-core/falcon/hal/ga102.rs | 4 ++--
drivers/gpu/nova-core/gfw.rs | 5 ++---
drivers/gpu/nova-core/util.rs | 8 +++-----
4 files changed, 13 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon.rs
index
07be1c30668c4bef9e073fe6ad49234aceb7fb81..f604e82c98120f2ab0f49b94be928967aa318df4
100644
--- a/drivers/gpu/nova-core/falcon.rs
+++ b/drivers/gpu/nova-core/falcon.rs
@@ -3,11 +3,11 @@
//! Falcon microprocessor base support
use core::ops::Deref;
-use core::time::Duration;
use hal::FalconHal;
use kernel::bindings;
use kernel::device;
use kernel::prelude::*;
+use kernel::time::Delta;
use kernel::types::ARef;
use crate::dma::DmaObject;
@@ -334,7 +334,7 @@ pub(crate) fn new(
/// Wait for memory scrubbing to complete.
fn reset_wait_mem_scrubbing(&self, bar: &Bar0) -> Result {
// TIMEOUT: memory scrubbing should complete in less than 20ms.
- util::wait_on(Duration::from_millis(20), || {
+ util::wait_on(Delta::from_millis(20), || {
if regs::NV_PFALCON_FALCON_HWCFG2::read(bar,
E::BASE).mem_scrubbing_done() {
Some(())
} else {
@@ -349,7 +349,7 @@ fn reset_eng(&self, bar: &Bar0) -> Result {
// According to OpenRM's `kflcnPreResetWait_GA102` documentation, HW
sometimes does not set
// RESET_READY so a non-failing timeout is used.
- let _ = util::wait_on(Duration::from_micros(150), || {
+ let _ = util::wait_on(Delta::from_micros(150), || {
let r = regs::NV_PFALCON_FALCON_HWCFG2::read(bar, E::BASE);
if r.reset_ready() {
Some(())
@@ -362,7 +362,7 @@ fn reset_eng(&self, bar: &Bar0) -> Result {
// TODO[DLAY]: replace with udelay() or equivalent once available.
// TIMEOUT: falcon engine should not take more than 10us to reset.
- let _: Result = util::wait_on(Duration::from_micros(10), || None);
+ let _: Result = util::wait_on(Delta::from_micros(10), || None);
regs::NV_PFALCON_FALCON_ENGINE::alter(bar, E::BASE, |v|
v.set_reset(false));
@@ -453,7 +453,7 @@ fn dma_wr<F: FalconFirmware<Target = E>>(
// Wait for the transfer to complete.
// TIMEOUT: arbitrarily large value, no DMA transfer to the
falcon's small memories
// should ever take that long.
- util::wait_on(Duration::from_secs(2), || {
+ util::wait_on(Delta::from_secs(2), || {
let r = regs::NV_PFALCON_FALCON_DMATRFCMD::read(bar, E::BASE);
if r.idle() {
Some(())
@@ -523,7 +523,7 @@ pub(crate) fn boot(
}
// TIMEOUT: arbitrarily large value, firmwares should complete in less
than 2 seconds.
- util::wait_on(Duration::from_secs(2), || {
+ util::wait_on(Delta::from_secs(2), || {
let r = regs::NV_PFALCON_FALCON_CPUCTL::read(bar, E::BASE);
if r.halted() {
Some(())
diff --git a/drivers/gpu/nova-core/falcon/hal/ga102.rs
b/drivers/gpu/nova-core/falcon/hal/ga102.rs
index
664327f75cf4199cca37d22ca18b2b9abac781f8..4e9af40fee914bfdf89588565d99503971c6af32
100644
--- a/drivers/gpu/nova-core/falcon/hal/ga102.rs
+++ b/drivers/gpu/nova-core/falcon/hal/ga102.rs
@@ -1,10 +1,10 @@
// SPDX-License-Identifier: GPL-2.0
use core::marker::PhantomData;
-use core::time::Duration;
use kernel::device;
use kernel::prelude::*;
+use kernel::time::Delta;
use crate::driver::Bar0;
use crate::falcon::{
@@ -23,7 +23,7 @@ fn select_core_ga102<E: FalconEngine>(bar: &Bar0) -> Result {
.write(bar, E::BASE);
// TIMEOUT: falcon core should take less than 10ms to report being
enabled.
- util::wait_on(Duration::from_millis(10), || {
+ util::wait_on(Delta::from_millis(10), || {
let r = regs::NV_PRISCV_RISCV_BCR_CTRL::read(bar, E::BASE);
if r.valid() {
Some(())
diff --git a/drivers/gpu/nova-core/gfw.rs b/drivers/gpu/nova-core/gfw.rs
index
ce03ac9f4d9d63cbfa91807c29efed16f1fa0cc8..d5b68e02d405750b18d634d772f15f413453e80d
100644
--- a/drivers/gpu/nova-core/gfw.rs
+++ b/drivers/gpu/nova-core/gfw.rs
@@ -6,10 +6,9 @@
//! the GPU is considered unusable until this step is completed, so we must
wait on it before
//! performing driver initialization.
-use core::time::Duration;
-
use kernel::bindings;
use kernel::prelude::*;
+use kernel::time::Delta;
use crate::driver::Bar0;
use crate::regs;
@@ -19,7 +18,7 @@
pub(crate) fn wait_gfw_boot_completion(bar: &Bar0) -> Result {
// TIMEOUT: arbitrarily large value. GFW starts running immediately after
the GPU is put out of
// reset, and should complete in less time than that.
- util::wait_on(Duration::from_secs(4), || {
+ util::wait_on(Delta::from_secs(4), || {
// Check that FWSEC has lowered its protection level before reading
the GFW_BOOT
// status.
let gfw_booted =
regs::NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK::read(bar)
diff --git a/drivers/gpu/nova-core/util.rs b/drivers/gpu/nova-core/util.rs
index
5cafe0797cd6f9567afb7e1e9af23b961a8a87f6..64fb137607643464ef579481fec19214f3556bd5
100644
--- a/drivers/gpu/nova-core/util.rs
+++ b/drivers/gpu/nova-core/util.rs
@@ -1,9 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
-use core::time::Duration;
-
use kernel::prelude::*;
-use kernel::time::Instant;
+use kernel::time::{Delta, Instant};
pub(crate) const fn to_lowercase_bytes<const N: usize>(s: &str) -> [u8; N] {
let src = s.as_bytes();
@@ -34,7 +32,7 @@ pub(crate) const fn const_bytes_to_str(bytes: &[u8]) -> &str {
///
/// TODO[DLAY]: replace with `read_poll_timeout` once it is available.
///
(https://lore.kernel.org/lkml/20250220070611.214262-8-fujita.tomon...@gmail.com/)
-pub(crate) fn wait_on<R, F: Fn() -> Option<R>>(timeout: Duration, cond: F) ->
Result<R> {
+pub(crate) fn wait_on<R, F: Fn() -> Option<R>>(timeout: Delta, cond: F) ->
Result<R> {
let start_time = Instant::now();
loop {
@@ -42,7 +40,7 @@ pub(crate) fn wait_on<R, F: Fn() -> Option<R>>(timeout:
Duration, cond: F) -> Re
return Ok(ret);
}
- if start_time.elapsed().as_nanos() > timeout.as_nanos() as i64 {
+ if start_time.elapsed().as_nanos() > timeout.as_nanos() {
return Err(ETIMEDOUT);
}
}
---
base-commit: 3606620b316c29e3de8ff87b40828c722086a9c9
change-id: 20250624-nova-delta-f2fecb58be8d
Best regards,
--
Alexandre Courbot <acour...@nvidia.com>
