Hi Prabhakar, > -----Original Message----- > From: Lad, Prabhakar <prabhakar.cse...@gmail.com> > Sent: 24 June 2025 16:16 > > > > There will be determine_clk followed by set_clock for setting new rate > > for PLL DSI(dsi->vclk * the divider value) For eg: vclk_max = 187.5 > > MHz, DSI Divider required = 16 Then set PLL_DSI = 187.5 * 16 MHz using > > clk_set. > > > This will trigger the algorithm twice, so I'll go with the current approach > which is optimal.
OK. Cheers, Biju
