On 6/25/25 15:55, Krzysztof Kozlowski wrote:
> On 25/06/2025 14:45, Michal Wilczynski wrote:
>>
>>
>> On 6/24/25 15:53, Matt Coster wrote:
>>> On 23/06/2025 12:42, Michal Wilczynski wrote:
>>>> Update the img,powervr-rogue.yaml to include the T-HEAD TH1520 SoC's
>>>> specific GPU compatible string.
>>>>
>>>> The thead,th1520-gpu compatible, along with its full chain
>>>> img,img-bxm-4-64, and img,img-rogue, is added to the
>>>> list of recognized GPU types.
>>>>
>>>> The power-domains property requirement for img,img-bxm-4-64 is also
>>>> ensured by adding it to the relevant allOf condition.
>>>>
>>>> Acked-by: Krzysztof Kozlowski <krzysztof.kozlow...@linaro.org>
>>>> Reviewed-by: Ulf Hansson <ulf.hans...@linaro.org>
>>>> Reviewed-by: Bartosz Golaszewski <bartosz.golaszew...@linaro.org>
>>>> Signed-off-by: Michal Wilczynski <m.wilczyn...@samsung.com>
>>>> ---
>>>> Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml | 9 ++++++++-
>>>> 1 file changed, 8 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
>>>> b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
>>>> index
>>>> 4450e2e73b3ccf74d29f0e31e2e6687d7cbe5d65..9b241a0c1f5941dc58a1e23970f6d3773d427c22
>>>> 100644
>>>> --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
>>>> +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
>>>> @@ -21,6 +21,11 @@ properties:
>>>> # work with newer dts.
>>>> - const: img,img-axe
>>>> - const: img,img-rogue
>>>> + - items:
>>>> + - enum:
>>>> + - thead,th1520-gpu
>>>> + - const: img,img-bxm-4-64
>>>> + - const: img,img-rogue
>>>> - items:
>>>> - enum:
>>>> - ti,j721s2-gpu
>>>> @@ -93,7 +98,9 @@ allOf:
>>>> properties:
>>>> compatible:
>>>> contains:
>>>> - const: img,img-axe-1-16m
>>>> + enum:
>>>> + - img,img-axe-1-16m
>>>> + - img,img-bxm-4-64
>>>
>>> This isn't right – BXM-4-64 has two power domains like BXS-4-64. I don't
>>> really know what the right way to handle that in devicetree is given the
>>> TH1520 appears to expose only a top-level domain for the entire GPU, but
>>> there are definitely two separate domains underneath that as far as the
>>> GPU is concerned (see the attached snippet from integration guide).
>>>
>>> Since power nodes are ref-counted anyway, do we just use the same node
>>> for both domains and let the driver up/down-count it twice?
>>
>> Hi Matt,
>>
>> Thanks for the very helpful insight. That's a great point, it seems the
>> SoC's design presents a tricky case for the bindings.
>>
>> I see what you mean about potentially using the same power domain node
>> twice. My only hesitation is that it might be a bit unclear for someone
>> reading the devicetree later. Perhaps another option could be to relax
>> the constraint for this compatible?
>>
>> Krzysztof, we'd be grateful for your thoughts on how to best model this
>> situation.
>
>
> It's your hardware, you should tell us, not me. I don't know how many
> power domains you have there, but for sure it is not one AND two domains
> the same time. It is either one or two, because power domains are not
> the same as regulator supplies.
Hi Krzysztof, Matt,
The img,bxm-4-64 GPU IP itself is designed with two separate power
domains. The TH1520 SoC, which integrates this GPU, wires both of these
to a single OS controllable power gate (controlled via mailbox and E902
co-processor).
This means a devicetree for the TH1520 can only ever provide one power
domain for the GPU. However, a generic binding for img,bxm-4-64 should
account for a future SoC that might implement both power domains.
That's why I proposed to relax the constraints on the img,bmx-4-64 GPU.
This makes the binding accurately represent the GPU's full capabilities
while remaining compatible with SoCs like the TH1520 that have a limited
implementation.
Does this seem like the correct and robust approach to you?
>
> Best regards,
> Krzysztof
>
Best regards,
--
Michal Wilczynski <m.wilczyn...@samsung.com>
