From: "shangyao.lin" <[email protected]> Add camera isp7x module device document.
--- Changes in v2: - Rename binding file to mediatek,mt8188-cam-raw.yaml - Various fixes per review comments - Update maintainers list Signed-off-by: shangyao.lin <[email protected]> --- .../mediatek/mediatek,mt8188-cam-raw.yaml | 156 ++++++++++++++++++ 1 file changed, 156 insertions(+) create mode 100755 Documentation/devicetree/bindings/media/mediatek/mediatek,mt8188-cam-raw.yaml diff --git a/Documentation/devicetree/bindings/media/mediatek/mediatek,mt8188-cam-raw.yaml b/Documentation/devicetree/bindings/media/mediatek/mediatek,mt8188-cam-raw.yaml new file mode 100755 index 000000000000..dfedb229e79c --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek/mediatek,mt8188-cam-raw.yaml @@ -0,0 +1,156 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (c) 2024 MediaTek Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek/mediatek,cam-raw.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: The cam-raw unit of MediaTek ISP system + +maintainers: + - Shangyao Lin <[email protected]> + - Shu-hsiang Yang <[email protected]> + - Shun-yi Wang <[email protected]> + - Teddy Chen <[email protected]> + +description: + MediaTek cam-raw is the camera RAW processing unit in MediaTek SoC. + +properties: + compatible: + const: mediatek,mt8188-cam-raw + + reg: + minItems: 1 + maxItems: 2 + description: + Base address and optional inner base address of the cam-raw hardware block. + + reg-names: + items: + - const: base + - const: inner_base + minItems: 1 + maxItems: 2 + description: + Names for each register region. Must be "base" and optionally "inner_base". + + mediatek,larbs: + description: + List of phandles to the local arbiters in the current SoCs. + Refer to bindings/memory-controllers/mediatek,smi-larb.yaml. + $ref: /schemas/types.yaml#/definitions/phandle-array + minItems: 1 + maxItems: 32 + + interrupts: + minItems: 1 + description: Interrupts for the cam-raw block. + + dma-ranges: + minItems: 1 + description: Address information of IOMMU mapping to memory. + + power-domains: + minItems: 1 + description: Power domains for the cam-raw block. + + clocks: + minItems: 4 + maxItems: 16 + description: List of phandles to the clocks required by the cam-raw block. + + clock-names: + items: + - const: camsys_cam2mm0_cgpdn + - const: camsys_cam2mm1_cgpdn + - const: camsys_cam2sys_cgpdn + - const: camsys_cam_cgpdn + - const: camsys_camtg_cgpdn + - const: camsys_rawa_larbx_cgpdn + - const: camsys_rawa_cam_cgpdn + - const: camsys_rawa_camtg_cgpdn + - const: topckgen_top_cam + - const: topckgen_top_camtg + - const: topckgen_top_camtm + minItems: 4 + maxItems: 16 + description: Names of the clocks, must match the order of the clocks property. + + iommus: + minItems: 1 + maxItems: 32 + description: Points to the respective IOMMU block with master port as argument. + +required: + - compatible + - reg + - reg-names + - interrupts + - power-domains + - clocks + - clock-names + - iommus + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/power/mediatek,mt8188-power.h> + #include <dt-bindings/clock/mediatek,mt8188-clk.h> + #include <dt-bindings/memory/mediatek,mt8188-memory-port.h> + + soc { + raw@16030000 { + compatible = "mediatek,mt8188-cam-raw"; + reg = <0 0x16030000 0 0x8000>, + <0 0x16038000 0 0x8000>; + reg-names = "base", "inner_base"; + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH 0>; + dma-ranges = <0x2 0x0 0x0 0x40000000 0x1 0x0>; + power-domains = <&spm MT8188_POWER_DOMAIN_CAM_SUBA>; + clocks = <&camsys CLK_CAM_MAIN_CAM2MM0_GALS>, + <&camsys CLK_CAM_MAIN_CAM2MM1_GALS>, + <&camsys CLK_CAM_MAIN_CAM2SYS_GALS>, + <&camsys CLK_CAM_MAIN_CAM>, + <&camsys CLK_CAM_MAIN_CAMTG>, + <&camsys_rawa CLK_CAM_RAWA_LARBX>, + <&camsys_rawa CLK_CAM_RAWA_CAM>, + <&camsys_rawa CLK_CAM_RAWA_CAMTG>, + <&topckgen CLK_TOP_CAM>, + <&topckgen CLK_TOP_CAMTG>, + <&topckgen CLK_TOP_CAMTM>; + clock-names = "camsys_cam2mm0_cgpdn", + "camsys_cam2mm1_cgpdn", + "camsys_cam2sys_cgpdn", + "camsys_cam_cgpdn", + "camsys_camtg_cgpdn", + "camsys_rawa_larbx_cgpdn", + "camsys_rawa_cam_cgpdn", + "camsys_rawa_camtg_cgpdn", + "topckgen_top_cam", + "topckgen_top_camtg", + "topckgen_top_camtm"; + iommus = <&vpp_iommu M4U_PORT_L16A_IMGO_R1>, + <&vpp_iommu M4U_PORT_L16A_CQI_R1>, + <&vpp_iommu M4U_PORT_L16A_CQI_R2>, + <&vpp_iommu M4U_PORT_L16A_BPCI_R1>, + <&vpp_iommu M4U_PORT_L16A_LSCI_R1>, + <&vpp_iommu M4U_PORT_L16A_RAWI_R2>, + <&vpp_iommu M4U_PORT_L16A_RAWI_R3>, + <&vpp_iommu M4U_PORT_L16A_UFDI_R2>, + <&vpp_iommu M4U_PORT_L16A_UFDI_R3>, + <&vpp_iommu M4U_PORT_L16A_RAWI_R4>, + <&vpp_iommu M4U_PORT_L16A_RAWI_R5>, + <&vpp_iommu M4U_PORT_L16A_AAI_R1>, + <&vpp_iommu M4U_PORT_L16A_UFDI_R5>, + <&vpp_iommu M4U_PORT_L16A_FHO_R1>, + <&vpp_iommu M4U_PORT_L16A_AAO_R1>, + <&vpp_iommu M4U_PORT_L16A_TSFSO_R1>, + <&vpp_iommu M4U_PORT_L16A_FLKO_R1>; + }; + }; + +... \ No newline at end of file -- 2.18.0
