On 11/06/2025 00:45, Chia-I Wu wrote: > On Mon, Jun 2, 2025 at 7:34 AM Karunika Choo <karunika.c...@arm.com> wrote: >> >> Mali-Gx20 and Mali-Gx25 deprecates the use of FLUSH_MEM and FLUSH_PT >> MMU_AS commands in favour of cache maintenance via >> GPU_COMMAND's FLUSH_CACHES and FLUSH_PA_RANGE. >> >> They also introduce the following registers: >> - GPU_COMMAND_ARG0~1 >> - SHADER_PWRFEATURES >> - AMBA_FEATURES >> - AMBA_ENABLE >> >> This patch enables FLUSH_CACHES for both families of GPUs via the >> PANTHOR_HW_FEATURE_GPU_CTRL_CACHE_FLUSH bit until FLUSH_PA_RANGE support >> is added. It also adds the aforementioned register definitions and >> firmware binary support for arch 12.8 and 13.8. > <snipped> >> diff --git a/drivers/gpu/drm/panthor/panthor_regs.h >> b/drivers/gpu/drm/panthor/panthor_regs.h >> index 4eaa2b612756..8e01440f8743 100644 >> --- a/drivers/gpu/drm/panthor/panthor_regs.h >> +++ b/drivers/gpu/drm/panthor/panthor_regs.h >> @@ -89,6 +89,8 @@ >> >> #define GPU_DOORBELL_FEATURES 0xC0 >> >> +#define GPU_COMMAND_ARG(n) (0xD0 + ((n) * 8)) >> + >> #define GPU_SHADER_PRESENT 0x100 >> #define GPU_TILER_PRESENT 0x110 >> #define GPU_L2_PRESENT 0x120 >> @@ -98,6 +100,8 @@ >> #define L2_READY 0x160 >> >> #define SHADER_PWRON 0x180 >> +#define SHADER_PWRFEATURES 0x188 >> +#define SHADER_PWRFEATURES_RAY_TRACING_UNIT BIT(0) >> #define TILER_PWRON 0x190 >> #define L2_PWRON 0x1A0 >> >> @@ -125,6 +129,13 @@ >> #define GPU_COHERENCY_ACE 1 >> #define GPU_COHERENCY_NONE 31 >> >> +#define AMBA_FEATURES 0x300 >> +#define AMBA_FEATURES_ACE_LITE BIT(0) >> +#define AMBA_FEATURES_ACE BIT(1) >> +#define AMBA_FEATURES_SHAREABLE_CACHE_SUPPORT BIT(5) >> + >> +#define AMBA_ENABLE 0x304 > We still use GPU_COHERENCY_FEATURES / GPU_COHERENCY_PROTOCOL even on > v12 and v13. I suppose they are compatible with AMBA_FEATURES / > AMBA_ENABLE to some degree? We should unify them. Hello,
Due to some changes in the fields between AMBA_ENABLE and GPU_COHERENCY_PROTOCOL, namely SHAREABLE_CACHE_SUPPORT, which has a value of BIT(5), the previous assumption that FEATURE = BIT(PROTOCOL) for GPU_COHERENCY_FEATURES is no longer valid. As such, I have updated the field Macros for GPU_COHERENCY_FEATURES to enable merging of the two register fields. Hopefully this addresses your comments. Kind regards, Karunika
